Patent Application
20240411331
Embodiments of the present disclosure generally relate to integrated circuit (IC) System-On-Chip (SoC) architectures, and in particular, to enhanced SoC voltage supply regulation to critical clock and data circuits of the IC.
In semiconductor manufacturing, a process corner is an example of a design technique that refers to variations of fabrication parameters when designing integrated circuits on a semiconductor wafer. Process corners represent the extremes of these parameter variations of the circuit fabricated on the semiconductor wafer that must function correctly. A circuit running on devices fabricated at these process corners may run slower or faster than specified and at lower or higher operating temperatures and/or voltages. A process corner represents a significant variation from nominal doping concentrations in transistors on the semiconductor wafer.
Front end of line (FEOL) process corners affect the performance of the semiconductor device. One naming convention for process corners uses two-letter designators, where the first letter refers to the N-channel metal oxide semiconductor field effect transistor (MOSFET) or NMOS corner, and the second letter refers to the P-channel (PMOS) corner. In this naming convention, three process corners exist: “typical,” “fast” and “slow.” Fast and slow corners exhibit a carrier mobility that is higher and lower, respectively, than a normal (typical). There are five possible corners: typical-typical (TT), fast-fast (FF), slow-slow (SS), fast-slow (FS), and slow-fast (SF). The first three corners (TT, FF, SS) are called even corners, because both types of devices are affected evenly, and generally do not adversely affect the logical operation of the circuit. The resulting devices can correctly operate at slower or faster clock frequencies, depending upon the supply voltage thereto.
In one example of the disclosure, an apparatus for on-chip integrated circuit voltage regulation includes a first voltage regulator having an input coupled to a reference voltage and an output providing a first regulated voltage. A bias voltage generator having an input coupled to the first regulated voltage and an output providing a bias voltage based upon process conditions of semiconductor devices of the integrated circuit. And a second voltage regulator having an input coupled to the bias voltage from the bias voltage generator and an output providing a second regulated voltage based upon the process conditions of the semiconductor devices of the integrated circuit.
In one example of the disclosure, an integrated circuit (IC) System-On-Chip (SoC) includes a plurality of on-chip integrated circuit voltage regulators adapted for providing optimal operating voltages to a plurality of digital logic circuits associated with the plurality of on-chip integrated circuit voltage regulators, wherein each of the plurality of on-chip integrated circuit voltage regulators comprises. A first voltage regulator having an input coupled to a reference voltage and an output providing a first regulated voltage. A bias voltage generator having an input coupled to the first regulated voltage and an output providing a bias voltage based upon process conditions of semiconductor devices of the integrated circuit. And a second voltage regulator having an input coupled to the bias voltage from the bias voltage generator and an output providing a second regulated voltage based upon the process conditions of the semiconductor devices comprising the digital circuits of the integrated circuit, wherein each pair of on-chip integrated circuit voltage regulators and digital logic circuits are located in different portions of the integrated circuit.
In one example of the disclosure, a method for adjusting an output voltage of an on-chip integrated circuit voltage regulator includes adjusting an output voltage of an on-chip integrated circuit voltage regulator based upon process conditions of the semiconductor devices of the integrated circuit, the output voltage is adapted for coupling to and powering the semiconductor devices of the integrated circuit. Raising the output voltage when the integrated circuit semiconductor devices are operating at a slow-slow (SS) process condition. And lowering the output voltage when the integrated circuit semiconductor devices are operating at a fast-fast (FF) process condition.
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to examples, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical examples of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective examples.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures, and a lower-case letter added where the elements are substantially the same. It is contemplated that elements of one embodiment may be beneficially incorporated in other embodiments.
With increased integration of System-On-Chip (SoC) architectures, the switching noise on the digital logic power supply poses detrimental effects on clock/data jitter performance thereof. Dealing with the clock/data jitter performance becomes more challenging as the data rates increase to higher levels. Besides higher data rates, the process variations also restrict system performance. Over the years, there have been myriad applications of local voltage supply regulation techniques implemented to improve the SoC system performance. Regulated supply voltages may be used in many locations in a semiconductor integrated circuit device. A clock tree is one such critical design where a dedicated voltage regulator supply is recommended.
Examples herein provide for use of a variable reference voltage to generate a regulated voltage supply for critical timing logic circuits of a SoC. The variable reference voltage is generated based on process and temperature conditions of the semiconductor integrated circuit devices (transistors) of the SoC. If the process condition is Slow N-Slow P (SS) and/or device temperatures are elevated, the reference voltage is set high and the voltage regulated supply is also set to a higher voltage. With the higher supply voltage, the semiconductor device performance (jitter/delay) is improved. If the semiconductor device is fabricated in Fast N-Fast P process conditions, a lower regulated voltage supply is good enough for the same performance as in typical-typical (TT) and slow-slow (SS) process conditions, and with the benefit of a reduced total power consumption budget.
Various features are described hereinafter with reference to the drawing figures. It should be noted that the drawing figures may or may not be drawn to scale and that the elements of similar structures or functions are represented by like reference numerals throughout the drawing figures. It should be noted that the drawing figures are only intended to facilitate the description of the features of the examples. They are not intended as an exhaustive description of the examples below or as a limitation on the scope of the claims. In addition, an illustrated example need not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular example is not necessarily limited to that example and can be practiced in any other examples even if not so illustrated, or if not so explicitly described. Referring now to the drawing figures, the details of examples are schematically illustrated. Like elements in the drawing figures will be represented by like numbers, and similar elements will be represented by like numbers with a different lower-case letter suffix.
Referring to
If the load devices 106 are operating in a Slow N-Slow P (SS) condition, there is high probability for inferior performance (delay and jitter) due to the higher MOSFET Vt of the load devices 106 in slow-slow operating conditions. In contrast, if the MOSFET devices are operating in a Fast N-Fast P condition, then performance metrics improve compared to Typical-Typical (TT) process conditions. The penalty paid is higher-power consumption due to lower Vt in Fast-Fast (FF) conditions. Providing the same performance as in the Typical-Typical (TT) process conditions, having a reduced total power consumption budget.
However, a problem exists when using a fixed voltage LDO voltage regulator, as shown in
Referring to
For example, the process and temperature dependent regulated supply voltage 230 may be boosted by, for example but is not limited to, 50 to 100 millivolts compared to a nominal supply voltage when the transistor devices of the logic load 206 operate in Slow-Slow conditions. By applying a higher supply voltage to Slow-Slow condition devices, and/or devices operating at a higher temperature, of a clock/data path will result in an improvement to the overall system performance, (e.g., delay and jitter). However, the maximum voltage value of the regulated supply voltage 230 should not exceed the voltage reliability limit of the devices of the associated logic load 206.
When the transistor devices of the logic load 206 operate in Fast-Fast conditions, the process and temperature dependent regulated supply voltage 230 may be lowered by, for example but is not limited to, 50 to 100 millivolts less than the nominal supply voltage. Lowering the supply voltage 230 also reduces power consumption of the logic load 206 when operating in Fast-Fast conditions while still maintaining overall system performance of the (FF) devices.
Referring to
A reference voltage (0.6V) 212 may be generated from a band gap reference voltage circuit (not shown) and is coupled to a negative input of the operational amplifier 202 of the LDO voltage regulator 302. An internal supply voltage 211, for example but not limited to 0.9V, will be constant if the band gap reference voltage 212 remains constant to the negative input of the operational amplifier 202. Voltage setting resistors 208 and 210 may be chosen based on the equation: 0.9 V=0.6 (1+R1/R2). The internal supply voltage 211 is coupled to the gate of the NMOS transistor 218 and to the source, through resistor R3, of the PMOS transistor 216.
In the process and temperature dependent bias voltage generator 302, the PMOS transistor 216 and NMOS transistor 218 are configured to adjust a process and temperature dependent bias voltage 214 based upon the process conditions of Fast-Fast, Typical-Typical or Slow-Slow of the semiconductor substrate in which the PMOS transistor 216 and NMOS transistor 218 are deposed. When the PMOS transistor 216 and NMOS transistor 218 are fabricated in a semiconductor die area resulting from a Slow-Slow process condition then the process and temperature dependent bias voltage 214 will be higher than when the semiconductor die area results from a Fast-Fast process condition. The PMOS transistor 216 and NMOS transistor 218 operate in their linear ranges.
The voltage regulator 306 uses the process and temperature dependent bias voltage 214 to adjust the voltage 230 supplied from the voltage regulator 306 to the logic load 206. The voltage regulator 306 may be configured as a LDO voltage regulator circuit, similar to the LDO voltage regulator 302, but with the feature of automatically adjusting the voltage 230 to optimize performance and power consumption of the logic load 206. When the process and temperature dependent bias voltage 214 goes up in value so will the voltage 230 from the voltage regulator 306, thus optimizing performance of semiconductor devices located in the same semiconductor die area at which PMOS transistor 216 and the NMOS transistor 218 of the process and temperature dependent bias voltage generator 304 are located.
It is contemplated and within the scope of this disclosure that any linear voltage regulator circuit could be used to function in the same fashion as the voltage regulator circuits 302 and 306 shown in
Referring to
Referring to
The input clock (Clk_in) frequency was one (1) GHz. The last stage of the (clock) inverter chain 502 drives (Clk_out) a wire load of 450 micrometers in length and 60 nanometers in width and spacing. Using SPICE simulations, different performance parameters were measured for the following two cases: Case 1—conventional LDO with a fixed input voltage reference, Case 2—the process and temperature dependent bias voltage generator 300 having temperature and process dependent variable voltage reference 214. Simulation corners: MOSFETs-5 (TT, SS3, FF3, SF3 and FS3), temperature low/high (−40° C. to 125° C.) resistors 2 (TT_RES, SS_RES and FF_RES). MOSFETS in 5 process conditions with 3-sigma variation: PMOS-Fast, NMOS-Fast; PMOS-Fast, NMOS-Slow; PMOS-Slow, NMOS-Slow; PMOS-Slow, NMOS-Fast; PMOS-Typical, NMOS-Typical. Resistor variation in 3—process conditions: Typical resistor, Fast resistor (30% less resistance than typical) and Slow resistor (30% more resistance than typical).
With the prior art configuration, propagation delay variation is about minus (−) 31 to 63 percent with reference to a nominal delay value. With the variable supply voltage examples disclosed herein, the propagation delay variation is about minus (−) 29 to 40 percent with reference to a nominal delay value. Control of the delay variation is improved by approximately 23 percent (63%-40%).
With the prior art configuration, the period jitter variation is minus (−) 44 to 190 percent with reference to a nominal period jitter value. With the variable supply voltage examples disclosed herein, the period jitter variation is about minus (−) 41 to 76 percent with reference to a nominal period jitter value. Jitter variation across process conditions is much improved with the variable supply voltage examples disclosed herein. There is a gain factor of about 114 percent (190%-76%).
With the prior art configuration, the rise time variation is about minus (−) 36 to 68 percent with reference to a nominal period jitter value. With the variable supply voltage examples disclosed herein, the period jitter variation is minus (−) 34 to 45 percent with reference to a nominal period jitter value. Rise time variation across process conditions is much improved with the variable supply voltage examples disclosed herein. There is a gain factor of about 23 percent (68%-45%). Critical parameters like jitter and delay are improved significantly with the variable supply voltage examples disclosed herein.
As will be appreciated by one skilled in the art and having the benefit of this disclosure, the embodiments disclosed herein may be embodied as a system, method, apparatus, or computer programmed product. Accordingly, aspects may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
