Claims
- 1. A process for forming a porous silicon membrane in a crystalline silicon member, comprising:
- masking at least a section of the silicon member,
- patterning an open area in the masked silicon member to expose the crystalline there under;
- electrochemical etching of the exposed crystalline silicon to form pores therein for forming the porous silicon membrane; and
- forming a means in the crystalline member selected from the group consisting of heater means and electrode means.
- 2. The method of claim 1, additionally including forming an opening in the crystalline silicon member adjacent the porous silicon membrane.
- 3. The method of claim 2, wherein the opening is formed prior to the electrochemical etching of the crystalline silicon.
- 4. The method of claim 1, additionally including forming a p++ back diffusion layer on a side of the crystalline silicon member opposite the masked section thereof.
- 5. The method of claim 1, additionally including providing a second substrate, forming a membrane in the second substrate, and bonding the substrates together such that the membrane in the second substrate is in an aligned, spaced relation to the thus formed porous silicon membrane.
- 6. The method of claim 5, additionally including providing the heating means adjacent the porous silicon membrane.
- 7. The method of claim 5, additionally including providing the electrode means located in spaced relation to said porous silicon membrane.
- 8. A process for forming a porous silicon membrane in a crystalline silicon member, comprising:
- masking at least a section of the silicon member,
- patterning an open area in the masked silicon member to expose the crystalline silicon there under;
- the masking and patterning of the crystalline silicon member being carried out to define a plurality of spaced exposed sections of the crystalline silicon member;
- electrochemical etching of the exposed crystalline silicon to form pores therein for forming the porous silicon membrane;
- the etching being carried out to form a plurality of porous spaced microchannels in the crystalline silicon member; and
- providing the plurality of spaced microchannels with a heater means to form a plurality of reaction chambers.
- 9. The method of claim 8, additionally including providing the plurality of spaced microchannels with positive and negative electrodes at opposite ends thereof to form a plurality of electrophoresis channels.
Parent Case Info
This application is a division of U.S. application Ser. No. 08/807,152 filed Feb. 27, 1997, now U.S. Pat. No. 5,882,496 issued Mar. 16, 1999.
Government Interests
The United States Government has rights in this invention pursuant to Contract No. W-7405-ENG-48 between the United States Department of Energy and the University of California for the operation of Lawrence Livermore National Laboratory.
US Referenced Citations (5)
Divisions (1)
|
Number |
Date |
Country |
Parent |
807152 |
Feb 1997 |
|