Claims
- 1. A single crystal silicon wafer having two major, generally parallel surfaces, one of which is the front surface of the wafer and the other of which is the back surface of the wafer, a central plane between the front and back surfaces, a circumferential edge joining the front and back surfaces, a stratum extending from the front surface to a distance, Ds, as measured from the front surface and toward the central plane, a surface layer which at least in part is coextensive with the stratum and which comprises the region of the wafer between the front surface and a distance, D1, of at least about 10 micrometers, as measured from the front surface and toward the central plane, and a bulk layer which comprises the region of the wafer between the central plane and the surface layer, the wafer being characterized in that
the wafer stratum is substantially free of agglomerated vacancy defects; and, the wafer has a non-uniform distribution of crystal lattice vacancies with the concentration of vacancies in the bulk layer being greater than the concentration of vacancies in the surface layer and with the vacancies having a concentration profile in which the peak density of the vacancies is at or near the central plane, the concentration generally decreasing from the position of peak density in the direction of the front surface of the wafer.
- 2. The wafer of claim 1 wherein Ds is at least about 5 micrometers.
- 3. The wafer of claim 1 wherein Ds is at least about 10 micrometers.
- 4. The wafer of claim 1 wherein Ds is at least about 20 micrometers.
- 5. The wafer of claim 1 wherein the concentration of interstitial oxygen at distances greater than 3 microns from the wafer surface is at least about 50% of the concentration of interstitial oxygen in the bulk layer.
- 6. The wafer of claim 1 wherein the concentration of interstitial oxygen at distances greater than 10 microns from the wafer surface is at least about 80% of the concentration of interstitial oxygen in the bulk layer.
- 7. The wafer of claim 1 wherein D1 is at least about 20 micrometers.
- 8. The wafer of claim 7 wherein Ds is at least about 5 micrometers.
- 9. The wafer of claim 7 wherein Ds is at least about 10 micrometers.
- 10. The wafer of claim 7 wherein Ds is at least about 20 micrometers.
- 11. The wafer of claim 7 wherein the concentration of interstitial oxygen at distances greater than 3 microns from the wafer surface is at least about 50% of the concentration of interstitial oxygen in the bulk layer.
- 12. The wafer of claim 7 wherein the concentration of interstitial oxygen at distances greater than 10 microns from the wafer surface is at least about 80% of the concentration of interstitial oxygen in the bulk layer.
- 13. The wafer of claim 1 wherein D1 is at least about 50 micrometers.
- 14. The wafer of claim 13 wherein Ds is at least about 5 micrometers.
- 15. The wafer of claim 13 wherein Ds is at least about 10 micrometers.
- 16. The wafer of claim 13 wherein Ds is at least about 20 micrometers.
- 17. The wafer of claim 13 wherein the concentration of interstitial oxygen at distances greater than 3 microns from the wafer surface is at least about 50% of the concentration of interstitial oxygen in the bulk layer.
- 18. The wafer of claim 13 wherein the concentration of interstitial oxygen at distances greater than 10 microns from the wafer surface is at least about 80% of the concentration of interstitial oxygen in the bulk layer.
- 19. The wafer of claim 1 further characterized in that the wafer has an epitaxial layer on the front surface of the wafer.
- 20. The wafer of claim 1 further characterized in that the front surface is polished.
- 21. The wafer of claim 1 further characterized in that the wafer has a carbon concentration of about 1×1016 atoms/cm3.
- 22. The wafer of claim 1 further characterized in that the wafer has a carbon concentration of about 5×1015 atoms/cm3.
- 23. The wafer of claim 1 further characterized in that the wafer has an absence of oxygen precipitate nucleation centers which are incapable of being dissolved by heat-treating the wafer at a temperature not in excess of about 1300° C.
- 24. The wafer of claim 1 wherein D1 is between about 30 and about 100 micrometers.
- 25. The wafer of claim 24 wherein Ds is between about 20 and about 100 micrometers.
- 26. A process for heat-treating a single crystal silicon wafer to dissolve agglomerated vacancy defects and to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step, the silicon wafer having two major, generally parallel surfaces, one of which is the front surface of the wafer and the other of which is the back surface of the wafer, a central plane between the front and back surfaces, a circumferential edge joining the front and back surfaces, a stratum extending from the front surface to a distance, Ds, measured from the front surface and toward the central plane, a surface layer which, at least in part is coextensive with the stratum and which comprises the region of the wafer between the front surface and a distance, D, measured from the front surface and toward the central plane, and a bulk layer which comprises the region of the wafer between the central plane and the surface layer, the process comprising:
thermally annealing the wafer in an atmosphere to dissolve pre-existing agglomerated vacancy defects in the stratum; heat-treating the annealed wafer to form crystal lattice vacancies in the surface and bulk layers; and, controlling the cooling rate of the heat-treated wafer to produce a wafer having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the wafer, the difference in the concentration of vacancies in the surface and bulk layers being such that a thermal treatment of the wafer at a temperature in excess of 750° C. is capable of forming a denuded zone in the surface layer and oxygen clusters or precipitates in the bulk layer with the concentration of the oxygen clusters or precipitates in the bulk layer being primarily dependant upon the concentration of vacancies.
- 27. The process of claim 26 wherein the wafer is thermally annealed in a hydrogen atmosphere.
- 28. The process of claim 26 wherein the wafer is thermally annealed in an argon atmosphere.
- 29. The process of claim 26 wherein the wafer is thermally annealed at a temperature between about 1100° C. and about 1300° C.
- 30. The process of claim 29 wherein the wafer is thermally annealed for about 1 to about 4 hours.
- 31. The process of claim 26 wherein the wafer is thermally annealed to dissolve pre-existing agglomerated vacancy defects in the stratum to a depth of about 10 micrometers.
- 32. The process of claim 26 wherein the wafer is thermally annealed to dissolve pre-existing agglomerated vacancy defects in the stratum to a depth of about 20 micrometers.
- 33. The process of claim 26 wherein the annealed wafer is heat-treated in a non-nitriding atmosphere.
- 34. The process of claim 33 wherein the atmosphere for said heat-treatment is primarily argon or helium.
- 35. The process of claim 26 wherein said cooling rate is at least about 50° C. per second through the temperature range at which crystal lattice vacancies are relatively mobile in silicon.
- 36. The process of claim 26 wherein said cooling rate is at least about 100° C. per second through the temperature range at which crystal lattice vacancies are relatively mobile in silicon.
- 37. The process of claim 26 wherein the annealed wafer is heat-treated in a nitriding atmosphere.
- 38. The process of claim 26 wherein the heat-treatment of the annealed wafer comprises heating the wafer to a temperature in excess of about 1175° C. in an oxygen containing atmosphere for a period of less than 60 seconds with the partial pressure of oxygen being less than about 5,000 ppma.
- 39. The process of claim 26 wherein the heat-treatment of the annealed wafer comprises heating the wafer to a temperature in excess of about 1200° C. in an oxygen containing atmosphere for a period of less than 60 seconds with the partial pressure of oxygen being less than about 5,000 ppma.
- 40. A process for heat-treating a single crystal silicon wafer to dissolve agglomerated vacancy defects and to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step, the silicon wafer having a front surface, a back surface, a central plane between the front and back surfaces, a stratum extending from the front surface to a distance, Ds, measured from the front surface and toward the central plane, a surface layer which, at least in part, is coextensive with the stratum and which comprises the region of the wafer between the front surface and a distance, D, measured from the front surface and toward the central plane, and a bulk layer which comprises the region of the wafer between the central plane and surface layer, the process comprising the steps of:
heat-treating the wafer in an atmosphere to form crystal lattice vacancies in the surface and bulk layers; controlling the cooling rate of the heat-treated wafer to produce a wafer having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the wafer and the difference in the concentration of vacancies in the surface and bulk layers being such that a thermal treatment of the wafer at a temperature in excess of 750° C. is capable of forming a denuded zone in the surface layer and oxygen clusters or precipitates in the bulk layer with the concentration of the oxygen clusters or precipitates in the bulk layer being primarily dependant upon the concentration of vacancies; stabilizing oxygen precipitate nucleation centers present in the cooled wafer by heating the cooled wafer to a temperature of about 650 to about 850° C. for about 1 hour to about 4 hours; and, thermally annealing the stabilized wafer in an atmosphere to dissolve agglomerated vacancy defects present within a region extending from the front surface to a depth of at least about 5 microns.
- 41. The process of claim 40 wherein the stabilized wafer is thermally annealed in a hydrogen atmosphere.
- 42. The process of claim 40 wherein the stabilized wafer is thermally annealed in an argon atmosphere.
- 43. The process of claim 40 wherein the stabilized wafer is thermally annealed at a temperature between about 1100° C. and about 1300° C.
- 44. The process of claim 43 wherein the stabilized wafer is thermally annealed for about 1 to about 4 hours.
- 45. The process of claim 40 wherein the stabilized wafer is thermally annealed to dissolve agglomerated vacancy defects within a region extending from the front surface to a depth of at least about 10 microns.
- 46. The process of claim 40 wherein the stabilized wafer is thermally annealed to dissolve agglomerated vacancy defects within a region extending from the front surface to a depth of at least about 20 microns.
- 47. The process of claim 40 wherein the wafer is heat-treated in a non-nitriding atmosphere.
- 48. The process of claim 47 wherein the atmosphere for said heat-treatment is primarily argon or helium.
- 49. The process of claim 40 wherein said cooling rate is at least about 50° C. per second through the temperature range at which crystal lattice vacancies are relatively mobile in silicon.
- 50. The process of claim 40 wherein said cooling rate is at least about 100° C. per second through the temperature range at which crystal lattice vacancies are relatively mobile in silicon.
- 51. The process of claim 40 wherein the wafer is heat-treated in a nitriding atmosphere.
- 52. The process of claim 40 wherein the wafer is heat-treated at a temperature in excess of about 1175° C. in an oxygen containing atmosphere for a period of less than 60 seconds with the partial pressure of oxygen being less than about 5,000 ppma.
- 53. The process of claim 52 wherein the stabilized wafer is thermally annealed to dissolve agglomerated vacancy defects within a region extending from the front surface to a depth of at least about 10 microns.
- 54. The process of claim 40 wherein the wafer is heat-treated at a temperature in excess of about 1200° C. in an oxygen containing atmosphere for a period of less than 60 seconds with the partial pressure of oxygen being less than about 5,000 ppma.
- 55. The process of claim 54 wherein the stabilized wafer is thermally annealed to dissolve agglomerated vacancy defects within a region extending from the front surface to a depth of at least about 10 microns.
REFERENCE TO RELATED APPLICATION
[0001] This application claims priority from U.S. provisional application Ser. No. 60/098,921, filed on Sep. 2, 1998.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60098921 |
Sep 1998 |
US |
Divisions (1)
|
Number |
Date |
Country |
Parent |
09385108 |
Aug 1999 |
US |
Child |
10067070 |
Feb 2002 |
US |