Claims
- 1. A process for producing time dependent waveforms of positive symmetrical sequence components (I1) and negative symmetrical sequence components (I2) of a power system's currents, comprising the steps of: sampling said power system's currents; and employing digital logic circuitry to generate digital symmetrical components (I1, I2) values in real time; wherein said digital logic circuitry comprises an arrangement of delay elements, amplifier elements and summing elements operatively interconnected to produce said digital symmetrical components in real time; and wherein said digital logic circuitry produces symmetrical components proportional to I1k and I2k, wherein I1 is a positive sequence current, I2 is a negative sequence current, and the subscript k is an index referring to digital samples of the respective components.
- 2. A process as recited in claim 1, wherein said digital logic circuitry produces Clarke components: ##EQU23## wherein said power system comprises a first phase (phase-a), a second phase (phase-b), and a third phase (phase-c), and Ia is a phase-a current, Ib is a phase-b current, and Ic is a phase-c current.
- 3. A process as recited in claim 2, wherein said digital logic circuitry receives samples of Ia, Ib and Ic; generates I.alpha..sub.k, I.alpha..sub.k-1, I.beta..sub.k and I.beta..sub.k-1 ; and then combines I.alpha..sub.k, I.alpha..sub.k-1, I.beta..sub.k and I.beta..sub.k-1 so as to produce values of I1.sub.k, I1.sub.k-1, I1.sub.k-2, I2.sub.k, I2.sub.k-1, and I2.sub.k-2.
- 4. A process as recited in claim 1, wherein said power system comprises a first phase (phase-a), a second phase (phase-b), and a third phase (phase-c), and said digital logic circuitry receives samples of Ia, Ib and Ic; generates sample values Ia.sub.k, Ia.sub.k-1, Ib.sub.k, Ib.sub.k-1, Ic.sub.k and Ic.sub.k-1 ; and then combines Ia.sub.k, Ia.sub.k-1, Ib.sub.k, Ib.sub.k-1, Ic.sub.k and Ic.sub.k-1 so as to produce values of I1.sub.k and I2.sub.k ; wherein Ia is a phase-a current, Ib is a phase-b current, and Ic is a phase-c current.
- 5. An apparatus for producing time dependent waveforms of positive symmetrical sequence components and negative symmetrical sequence components of a power system's voltages or currents, comprising:
- (a) means for sampling said power system's currents; and
- (b) digital logic circuitry for generating positive symmetrical sequence components (I1) and negative symmetrical sequence components (I2) of a power system's currents, comprising an arrangement of delay elements, amplifier elements and summing elements operatively interconnected to produce said digital symmetrical components in real time; wherein said digital logic circuitry produces symmetrical components proportional to I1k and I2k, wherein I1 is a positive sequence current, I2 is a negative sequence current, and the subscript k is an index referring to digital samples of the respective components.
- 6. An apparatus as recited in claim 5, wherein said power system comprises a first phase (phase-a), a second phase (phase-b), and a third phase (phase-c), and said digital logic circuitry produces Clarke components: ##EQU24## wherein Ia is a phase-a current, Ib is a phase-b current, and Ic is a phase-c current.
- 7. An apparatus as recited in claim 6, wherein said digital logic circuitry comprises a first input terminal for receiving samples of Ia, a second input terminal for receiving samples of Ib, a third input terminal for receiving samples of Ic; means for generating I.alpha..sub.k, I.alpha..sub.k-1, I.beta..sub.k and I.beta..sub.k-1 ; and means for combining I.alpha..sub.k, I.alpha..sub.k-1, I.beta..sub.k and I.beta..sub.k-1 so as to produce values of I1.sub.k, I1.sub.k-1, I1.sub.k-2, I2.sub.k, I2.sub.k-1, and I2.sub.k-2.
- 8. An apparatus as recited in claim 5, wherein said power system comprises a first phase (phase-a), a second phase (phase-b), and a third phase (phase-c), and said digital logic circuitry comprises a first input terminal for receiving samples of Ia, a second input terminal for receiving samples of Ib, a third input terminal for receiving samples of Ic; means for generating sample values Ia.sub.k, Ia.sub.k-1, Ib.sub.k, Ib.sub.k-1, Ic.sub.k and Ic.sub.k-1 ; and means for combining Ia.sub.k, Ia.sub.k-1, Ib.sub.k, Ib.sub.k-1, Ic.sub.k and Ic.sub.k-1 so as to produce values of I1.sub.k and I2.sub.k ; wherein Ia is a phase-a current, Ib is a phase-b current, and Ic is a phase-c current.
RELATED APPLICATIONS
This is a continuation of application Ser. No. 08/453,236, filed May 30, 1995, now abandoned, which is a division of Ser. No. 08/326,720, filed Oct. 20, 1994, now entitled: A Process and Apparatus for Comparing in Real Time Phase Differences Between Phasors, and now U.S. Pat. No. 5,576,618, issued on Nov. 19, 1996.
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Divisions (1)
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Number |
Date |
Country |
Parent |
326720 |
Oct 1994 |
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Continuations (1)
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Number |
Date |
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Parent |
453236 |
May 1995 |
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