Claims
- 1. A process for displaying data, during a frame, on a matrix screen having a first part and a second part, each said part having an even plurality of rows of number N, each said plurality of rows of each said part being organized into two pluralities of rows, a first plurality having a first parity and a second plurality having a second parity different from said first parity, each said part also having a plurality of independently addressable columns M, each said column of said first part crossing over all of the rows of said first part, each said column of said second part crossing over all of the rows of said second part, individual pixels of said screen being defined by points at which said columns cross over said rows, said frame to be displayed being divided into a first half-frame and second half-frame, said process comprising the steps of:
- a. successively selecting, during said first half-frame, successive rows of said first parity of said first part, while simultaneously successively selecting successive rows of said second parity of said second part that are paired with said successive rows of said first parity of said first part;
- b. successively selecting, during said second half-frame successive rows of said second parity of said first part, while simultaneously successively selecting successive rows of said first parity of said second part that are paired with said successive rows of said second parity of said first part; and
- c. displaying on rows selected during steps a and b, data supplied from a memory means and a video source with a regular timing and in an order related to successive rows of the screen, selection of said rows taking place at twice said regular timing, wherein during step a, data displayed on the rows of said first parity of said first part are supplied from the source and data displayed on the rows of said second parity of said second part are supplied from said memory means, and wherein during step b, data displayed on the rows of said second parity of said first part are supplied from said memory means and data displayed on the rows of said first parity of said second part are supplied from the source, the data supplied from said memory means during said first half-frame having been supplied from said source and stored in said memory means during a preceding half-frame, and the data supplied from said memory means during said second half-frame having been supplied from said source and stored in said memory means during said first half-frame, said memory means having a capacity for storing about one-fourth of the data displayed on said matrix screen during said frame.
- 2. A process according to claim 1, wherein:
- i. during the supply of said data in a memory are recorded the data to be displayed on the rows of the second parity;
- ii. parallel to each selection of a row of the first part paired with a row of the second part, each selection starting synchronously with the supply by the source of the data to be displayed on a row of the first parity,
- a. in a first register is recorded from a first buffer register the data to be displayed on said selected row of the first part,
- b. in a second register are recorded from a second buffer register the data to be displayed on said selected row of the second part,
- c. the data supplied by the source and to be displayed on the row of said first parity of the following selection are recorded in the buffer register associated with said row,
- d. the data to be displayed on the second parity row of the following selection are transferred from the memory into the buffer register associated with said row.
- 3. Apparatus for displaying data, during a frame, on a matrix screen having a first part and a second part, each said part having an even plurality of rows of number N and a plurality of independently addressable columns M, each said plurality of rows of each part being organized into two pluralities of rows, a first plurality having a first parity and a second plurality having a second parity different from said first parity, said frame to be displayed being divided into a first half-frame and a second half-frame, said apparatus being capable of performing the process of claim 1, and comprising, a source for supplying on an output the data to be displayed,
- a memory for recording alternatively the data to be displayed on the rows of the second parity of each part of the screen and being connected to the output of the source,
- means for controlling the writing and reading of the memory and connected to said memory,
- means for generating the writing and reading addresses and connected to said memory,
- first switching means connected both to the output of the source and to an output of said memory,
- means for controlling the switching of the first switching means and connected to said first switching means,
- second switching means connected to both the output of the source and to the output of said memory,
- means for controlling the switching of the second switching means and connected to the latter,
- a first buffer register connected to an output of the first switching means,
- a second buffer register connected to an output of the second switching means, and
- a first register connected to an output of the first buffer register for supplying the data to be displayed on a select of the first part of the screen, a second register connected to data output of the second buffer register for supplying the data to be displayed on a selected row of the second part of the screen simultaneously with the display of said data on said first part, and wherein each said column of said first part crosses over all of the rows of said first part, each said column of said second part crosses over all of the rows of said second part, and individual pixels of said screen are defined by points at which said columns cross over said rows.
- 4. Apparatus according to claim 3, wherein the memory has sufficient storage to simultaneously contain the data to be displayed on N/2 screen rows.
- 5. Apparatus according to claim 4, wherein the writing and reading control means of the memory comprises a counter having two binary states having counting input for receiving a pulse signal synchronized with the supply of the data to be displayed on a row and a second input for receiving a resetting signal, said counter supplying on one output a pulse for each transition to its initial state and on another output connected to the memory a control signal.
- 6. Apparatus according to claim 5, wherein the means for producing writing and reading addresses comprises a counter with N/2 binary states having a counting input connected to the output of the counter with two binary states supplying pulses upon each transition to its initial state and a second input for receiving a resetting signal, said counter supplying on one output a pulse upon each transition to its initial state and on another output connected to the memory an address signal.
- 7. Apparatus according to claim 6, wherein the first and second means for controlling the switching of the first and second switching means comprise a single circuit.
- 8. Apparatus according to claim 7, wherein said single circuit is a counter having two binary states with a counting input connected to the output of the counter with N/2 binary states and supplying on an output a pulse upon each transition to its initial state and a second input for receiving a resetting signal, said counter supplying to an output connected to the first and second switching means a control signal.
- 9. Apparatus according to claim 3, and further comprising, for selecting the screen rows, at least one register having a first input for receiving a clock signal and a second input for receiving a data signal.
- 10. Apparatus according to claim 9, and further comprising a first register with N stages for the selection of N rows of the first parity of the first and second parts of the screen and having a first input for receiving a clock signal and a second input for receiving a first data signal and second register having N stages for the selection of N rows of the second parity of the first and second parts of the screen and having a first input for receiving the clock signal and second input for receiving a second data signal.
Priority Claims (1)
Number |
Date |
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Kind |
90 01346 |
Feb 1990 |
FRX |
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Parent Case Info
This is a continuation of application Ser. No. 08/028,686 filed on Mar. 8, 1993, which is a continuation of application Ser. No. 07/646,703 filed on Jan. 25, 1991, now both abandoned.
US Referenced Citations (10)
Foreign Referenced Citations (1)
Number |
Date |
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0195203 |
Sep 1986 |
EPX |
Continuations (2)
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Number |
Date |
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Parent |
28686 |
Mar 1993 |
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Parent |
646703 |
Jan 1991 |
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