Patent Grant
9609410
Technical Field
The present disclosure relates to a processing circuit for a digital microelectromechanical sensor, which includes two or more sensing structures and has a broad dynamic range. In addition, the present disclosure relates to a sensor that includes the aforementioned processing circuit.
Description of the Related Art
As is known, there are today available acoustic transducers such as, for example, the so-called MEMS (microelectromechanical systems) microphones, each of which comprises a sensing structure of a MEMS type, which is also known as “detection structure” and is designed to transduce acoustic pressure waves into an electrical quantity (for example, a capacitive variation), and a reading electronics, designed to carry out appropriate operations of processing of this electrical quantity, for supplying an electrical output signal, whether analog (for example, a voltage) or digital; in the latter case, the microphone is a digital microphone. For instance, with particular reference to electrical output signals of a digital type, MEMS microphones are known that supply signals of a so-called “PDM” (pulse-density modulation) type.
The electrical output signal is then made available, possibly after prior further processing by an electronic interface circuit, to an external electronic system, such as for example a microcontroller of an electronic apparatus that incorporates the MEMS microphone.
In the case of MEMS acoustic transducers of a capacitive type, each sensing structure comprises a fixed electrode and a mobile electrode, which is formed by a diaphragm or membrane and is arranged facing the fixed electrode, so that the fixed electrode and the mobile electrode form the plates of a sensing capacitor with variable capacitance. The sensing capacitor is typically connected to a charge pump, which performs the task of maintaining the charge present on the sensing capacitor itself constant.
More in particular, a perimetral portion of the mobile electrode is typically anchored to a substrate, whereas a central portion of the mobile electrode is free to move following upon incidence of an acoustic signal, i.e., a pressure wave. Consequently, at least a part of the mobile electrode is arranged in oscillation by the acoustic signal, with consequent variation of the capacitance of the sensing capacitor.
An example of a sensing structure of a MEMS microphone of a capacitive type is described in US Patent Publication No. 2010/0284553 filed in the name of the present applicant.
In general, the electrical performance of a MEMS microphone depends upon the mechanical characteristics of the sensing structure, and further upon the configuration of the acoustic chambers formed by the sensing structure; in this connection, the sensing structure forms a front chamber and a rear chamber, which face, respectively, the front face and the rear face (opposite to one another) of the mobile electrode and are traversed, in use, by the pressure waves that impinge upon the sensing structure.
From a more quantitative standpoint, it is possible to characterize a sensing structure in terms of sensitivity and dynamics, the latter quantity being also known as “dynamic range”.
The dynamic range indicates the sound-pressure levels (SPL) of the acoustic signals that may be correctly demodulated by the sensing structure. Consequently, the upper bound of the dynamic range indicates the sound-pressure level beyond which a saturation of the response of the sensing structure occurs, whereas the lower bound indicates the noise level, i.e., the sound-pressure level below which the acoustic signal is not detected.
The sensitivity is instead proportional to the ratio between the variation of the aforementioned electrical quantity (for example, the capacitance of the sensing capacitor) and the corresponding variation of the sound-pressure level.
This having been said, there are numerous applications in which there are used both a broad dynamic range, i.e., the possibility of detecting acoustic signals that have sound-pressure levels markedly different from one another, and a high sensitivity. Unfortunately, however, typically the sensing structures that have a high sensitivity are characterized also by narrow dynamic ranges, and vice versa. In addition, typically the sensing structures that have broad dynamic ranges are characterized by not particularly high signal-to-noise ratios (SNRs).
In this connection, U.S. Pat. No. 6,271,780 describes a solution for increasing the dynamic range, which envisages subjecting an analog input signal to two processing paths, each of which comprises a first, analog, portion and a second, digital, portion; further, each processing path is characterized by its own gain. The digital signals at output from the two processing paths are recombined to supply a resulting output signal. Before the two digital signals are recombined, they are subjected to operations of equalization for compensating for the differences present between the two processing paths, but for the different gains, in order to limit the distortions present on the resulting output signal.
The solution proposed in U.S. Pat. No. 6,271,780 is not free from problems, linked principally to the complexity of the processing chain, and thus to the dimensions of the area used for implementing this solution. In addition, this solution envisages that, starting from a single input signal, two intermediate signals are generated, which are then mixed to form an output signal.
One embodiment of the present disclosure is directed to a processing circuit for a digital sensor, that includes a control stage configured to generate a control signal, a multiplexing stage electrically coupled to a plurality of external signal sensing structures and configured to receive respective detection signals from said sensing structures, said multiplexing stage being configured to generate a multiplexed signal, on the basis of one of said detection signals, as a function of the control signal, an analog-to-digital conversion stage, coupled to the multiplexing stage and configured to generate a first encoded signal, on the basis of the multiplexed signal, and an equalizer, configured to multiply the first encoded signal by a coefficient that depends upon the control signal.
For a better understanding of the present disclosure, preferred embodiments thereof are now described, purely by way of non-limiting example and with reference to the annexed drawings, wherein:
The present processing circuit is described in what follows, without this implying any loss of generality, with reference to a digital microphone 1 illustrated in
In detail, the digital microphone 1 comprises a first sensing structure 2a and a second sensing structure 2b, of a per se known type. In what follows, it is assumed, without this implying any loss of generality, that the first and second sensing structures 2a, 2b are MEMS sensing structures of a capacitive type for acoustic transducers. The first and second sensing structures 2a, 2b are represented schematically in
Each of the first and second sensing structures 2a, 2b may comprise a respective membrane, designed to undergo deformation as a function of the incident acoustic signals. In addition, the first and second sensing structures 2a, 2b present different mechanical characteristics, for example in terms of different rigidity to deformation, which determine different electrical characteristics as regards the capacity of detecting acoustic signals.
In detail, the first and second sensing structures 2a, 2b have different sensitivities and dynamic ranges. Without this implying any loss of generality, in what follows it is assumed that the first and second sensing structures 2a, 2b have, respectively, a first sensitivity S1 and a second sensitivity S2, as well as a first dynamic range I1 and a second dynamic range I2, the upper bounds of which are, respectively, Imax1 and Imax2. Without this implying any loss of generality, it is assumed that the first and second dynamic ranges I1, I2 partially overlap and that the first and second sensitivities S1, S2 are substantially constant within the first dynamic range I1 and the second dynamic range I2, respectively.
It is likewise assumed, once again by way of example, that the relations S1>S2 and Imax1<Imax2 apply; in other words, it is assumed that the first sensing structure 2a is designed to transduce signals that have low sound-pressure levels, and that the second sensing structure 2b is designed to transduce signals that have high sound-pressure levels. Purely by way of example, the first and second sensing structures 2a, 2b may be configured to detect signals that have maximum sound-pressure levels with acoustic overload point (AOP) for example equal to 120 dBSPL and 140 dBSPL, respectively. It is further possible, without this implying any loss of generality, for the first and second dynamic ranges I1, I2 to have the same breadth.
As described in greater detail hereinafter, the first and second sensing structures 2a, 2b may be formed, purely by way of example, by two portions of the same membrane, facing respective fixed electrodes, for forming two sensing capacitors. In this case, one of these two portions is a peripheral portion of the membrane, which is designed to detect signals with high sound-pressure levels, whereas the other is a central portion of the membrane, which undergoes greater elastic deformations and is thus designed to detect signals with low sound-pressure levels, given its higher sensitivity.
Irrespective of the details of implementation of the first and second sensing structures 2a, 2b, when an acoustic signal impinges upon the first and second sensing structures 2a, 2b, the latter supply at output, respectively, a first detection signal sd1(t) and a second detection signal sd2(t), of an analog type. For instance, the first and second detection signals sd1(t), sd2(t) may be voltage signals. In addition, the first detection signal sd1(t) has an amplitude greater than that of the second detection signal sd2(t).
The digital microphone 1 further comprises a processing circuit 3, which comprises a first amplification stage 6a and a second amplification stage 6b, which have inputs connected to the outputs of the first and second sensing structures 2a, 2b, respectively.
The first and second amplification stages 6a, 6b have a first gain G1 and a second gain G2, respectively, and supply on the respective outputs a first input signal sin1(t) and a second input signal sin2(t). In addition, it is found that S1·G1>S2·G2; in particular, without this implying any loss of generality, in what follows it is assumed that S1·G1=32·S2·G2.
The processing circuit 3 further comprises a multiplexer 8 having two signal inputs, a control input, and an output, the two signal inputs being, respectively, connected to the outputs of the first and second amplification stages 6a, 6b. In use, the multiplexer 8 is designed to supply on its own output a multiplexed signal smux(t), which is alternatively equal to the first input signal sin1(t) or else to the second input signal sin2(t), as a function of a control signal sc(n), present on the control input and described in greater detail hereinafter. In other words, as described in what follows, it is found that portions of the multiplexed signal smux(t) are equal to corresponding portions of the first input signal sin1(t), whereas other portions of the multiplexed signal smux(t) are equal to corresponding portions of the second input signal sin2(t).
The processing circuit 3 likewise comprises a first converter 10 of an analog-to-digital type. In particular, the first converter 10 is a so-called sigma-delta converter, of a per se known type, designed to receive at input the multiplexed signal smux(t) and to supply at output a first PDM signal sPDM1(n). In what follows, the first converter 10 is referred to as “first sigma-delta converter 10”.
In detail, without this implying any loss of generality, the first sigma-delta converter 10 carries out a conversion according to the diagram illustrated in
In greater detail, the input filter 12 is of a low-pass type and functions as anti-aliasing filter. In addition, the input filter 12 has an output and an input, the latter being connected to the output of the multiplexer 8 so that the input filter 12 receives the multiplexed signal smux(t) and supplies on the respective output a signal to be processed sproc(t). In particular, the input filter 12 is such that the signal to be processed sproc(t) has a frequency band equal to f0.
The sample-and-hold 14 has a respective input connected to the output of the input filter 12 and operates at a sampling frequency fs, for example equal to 3.072 MHz; consequently, the sample-and-hold 14 supplies on a respective output a sampled signal ssample(n). More in particular, we have fs/2>f0 so that the sample-and-hold 14 carries out an oversampling of the signal to be processed sproc(t).
The first adder 16 has an output, and a first input and a second input; the first input is connected to the output of the sample-and-hold 14. In addition, the first adder 16 supplies on its own output a first difference signal sdiff1(n), which, as described hereinafter, is equal to the difference between the two signals present on its own first and second inputs.
The first loop filter 18 is of a digital type and has an input and an output, the input being connected to the output of the first adder 16. In addition, the first loop filter 18 supplies on its own output a first processed signal sint1(n).
Purely by way of example, the first loop filter 18 may be formed by an integrator, in which case the first sigma-delta converter 10 is of the first order; however possible are embodiments in which the first sigma-delta converter 10 is of a higher order. For instance, without this implying any loss of generality, embodiments are possible in which the first sigma-delta converter 10 is of the fourth order, in which case it has a corresponding block structure, of a per se known type.
The first quantizer 20 has an input and an output, which are, respectively, connected to the output of the first loop filter 18 and to the second input of the first adder 16. In addition, the first quantizer 20 supplies on its own output a first quantized signal, referred to as first PDM signal sPDM1(n).
Thus, given the feedback described, we have sdiff1(n)=ssample(n)−sPDM1(n). Without this implying any loss of generality, in what follows it is assumed that the first quantizer 20 is a single-bit quantizer, and thus that the first PDM signal sPDM1(n) is formed by a stream of samples, each encoded on a single bit. In practice, the first PDM signal sPDM1(n) is formed by a PDM bitstream.
In a per se known manner, the first sigma-delta converter 10 thus converts the multiplexed signal smux(t) into the first PDM signal sPDM1(n).
The processing circuit 3 further comprises an encoder 28, which has an output and an input, the latter being connected to the output of the first sigma-delta converter 10, and in particular to the output of the first quantizer 20. The encoder 28 then receives the first PDM signal sPDM1(n) and supplies on its own output a first encoded signal scode1(n).
Without this implying any loss of generality, the first encoded signal scode1(n) is formed in the following way. For each bit of the first PDM signal sPDM1(n) present at input to the encoder 28, the encoder 28 supplies on its own output a pair of bits equal to:
In practice, the first encoded signal scode1(n) is a two's complement representation of a stream of samples such that, for each bit of the first PDM signal sPDM1(n), the stream of samples includes a corresponding sample equal to 1 if the bit of the first PDM signal SPDM1(n) is “1”, or else equal to −1 if the bit of the first PDM signal sPDM1(n) is “0”.
The processing circuit 3 further comprises an equalizer 30, which has a signal input, a control input, a first additional input and a second additional input, and an output; further, the processing circuit 3 comprises a first memory block 31a and a second memory block 31b, which store a first coefficient DIV1 and a second coefficient DIV2, respectively.
In what follows, it is assumed, purely by way of example, that the first and second coefficients DIV1, DIV2 are, respectively, equal to 1/32 and 1. In addition, it is assumed, without this implying any loss of generality, that that the following relation applies: S1·G1·DIV1=S2·G2·DIV2.
In detail, the signal input of the equalizer 30 is connected to the output of the encoder 28, whereas the first and the second additional inputs are connected to the first memory block 31a and to the second memory block 31b, respectively. Without this implying any loss of generality, it is assumed that the connection between the output of the encoder 28 and the signal input of the equalizer 30 is of a parallel type so that the encoder 28 generates the aforementioned pairs of bits at a frequency equal to the sampling frequency fs.
Present on the control input of the equalizer 30 is the aforementioned control signal sc(n).
In use, the equalizer 30 supplies on its own output a second encoded signal scode2(n), as a function of the first encoded signal scode1(n) and according to one between the first and second coefficients DIV1, DIV2. In particular, the equalizer 30 selects, as described hereinafter, a coefficient between the first and second coefficients DIV1, DIV2 and determines the samples of the second encoded signal scode2(n) on the basis of the samples of the first encoded signal scode1(n) and of the coefficient selected.
In detail, for each of the samples of the first PDM signal sPDM1(n), and thus for each pair of consecutive bits of the first encoded signal scode1(n), the equalizer 30 generates a corresponding sample, which is encoded with two's complement on a number of bits for example equal to seven. In addition, without this implying any loss of generality, the frequency at which the samples of the second encoded signal scode2(n) are generated is equal to the sampling frequency fs; consequently, the output of the equalizer 30 is of a parallel and thus multibit type.
As illustrated in greater detail in
In other words, the first six bits of the aforementioned set of seven bits are equal to the bit that indicates the sign within the two's complement notation of the first encoded signal scode1(n). In addition, assuming that the second, third, fourth, fifth, sixth, and seventh bits of the set of seven bits are associated to weights, respectively, equal to 20, 2−1, 2−2, 2−3, 2−4, and 2−5, we have that the sample of the second encoded signal scode2(n), which is encoded in fixed-point two's complement by the aforementioned set of seven bits, is alternatively equal to 1/32 (if the pair of bits of the first encoded signal scode1(n) is equal to “01”) or − 1/32 (if the pair of bits of the first encoded signal scode1(n) is equal to “11”).
In addition, if the coefficient selected is the second coefficient DIV2 (
In other words, the first of the seven bits is equal to the bit that indicates the sign within the two's complement notation of the first encoded signal scode1(n). In addition, assuming once again that the second, third, fourth, fifth, sixth, and seventh bits of the set of seven bits are associated to weights, respectively, equal to 20, 2−1, 2−2, 2−3, 2−4, and 2−5, we have that the sample of the second encoded signal scode2(n), which is once again encoded in fixed-point two's complement by the aforementioned set of seven bits, is alternatively equal to 1 (if the pair of bits of the first encoded signal scode1(n) is equal to “01”) or −1 (if the pair of bits of the first encoded signal scode1(n) is equal to “11”).
In practice, the equalizer 30 operates as a numeric divider, since it carries out a two's complement binary division, where the divisor is alternatively equal to 1/DIV1 or else 1/DIV2 and is selected on the basis of the control signal sc(n), as described in detail in what follows.
The processing circuit 3 further comprises a second converter 40 of the digital-to-digital type. In particular, the second converter 40 is a so-called sigma-delta converter, of a per se known type, designed to receive at input the second encoded signal scode2(n) and to supply at output a second PDM signal sPDM2(n). In what follows, the second converter 40 is referred to as “second sigma-delta converter 40”.
Without this implying any loss of generality, the second sigma-delta converter 40 carries out a conversion according to the scheme illustrated in
In greater detail, the second adder 46 has an output and a first input and a second input; the first input is connected to the output of the equalizer 30 for receiving the second encoded signal scode2(n).
In addition, the second adder 46 supplies on its own output a second difference signal sdiff2(n), which, as described hereinafter, is equal to the difference between the two signals present on its own first and second inputs. In the embodiment described, the samples of the second difference signal sdiff2(n) are encoded in fixed-point two's complement, on seven bits.
The second loop filter 48 is of a digital type and has an input and an output, the input being connected to the output of the second adder 46. In addition, the second loop filter 48 filters the samples of the second difference signal sdiff2(n) and supplies on its own output a second processed signal sint2(n). Purely by way of example, the second loop filter 48 may be formed by an integrator, in which case the second sigma-delta converter 40 is of the first order; however possible are embodiments in which the second sigma-delta converter 40 is of a higher order, for example equal to four, in which case it has a corresponding block structure, of a per se known type.
The second quantizer 50 has an input and an output, which are, respectively, connected to the output of the second loop filter 48 and to the second input of the second adder 46. In addition, the second quantizer 50 supplies on its own output a second quantized signal, referred to hereinafter as “second PDM signal sPDM2(n)”. Consequently, given the feedback described, we have sdiff2(n)=scode2(n)−sPDM2(n).
Without this implying any loss of generality, in what follows it is assumed that the second quantizer 50 is a single-bit quantizer, and thus that the second PDM signal sPDM2(n) is formed by a stream of samples, each encoded on a single bit; these samples are supplied at a frequency equal to the sampling frequency fs. It is further assumed that, in order to calculate sdiff2(n)=scode2(n)−sPDM2(n), the second adder 46 will convert the samples of the second PDM signal sPDM2(n) for encoding them in fixed-point two's complement, on seven bits.
In practice, the second sigma-delta converter 40 converts the second encoded signal scode2(n), where the samples are encoded on a number of bits, into the second PDM signal sPDM2(n), where each sample is encoded on a single bit.
The processing circuit 3 further comprises a processing stage 70, which in turn comprises a decimation filter 72, the input of which is connected to the output of the equalizer 30 for receiving the second encoded signal scode2(n). On its own output, the decimation filter 72 supplies a decimated signal sdec(n).
In detail, the decimation filter 72, for example, has a pulse response of a so-called “sinc function” type, the order of which may, for example, be equal to K+1, where K is the order of the first converter 10. In addition, the decimation filter 72 decimates the samples of the second encoded signal scode2(n); for example, the decimation filter 72 may discard three samples out of four of the second encoded signal scode2(n), in which case the samples of the decimated signal sdec(n) are supplied at a frequency equal to one quarter of the sampling frequency fs, the output of the decimation filter 72 being again of a parallel type. For practical purposes, the decimation filter 72 removes the quantization noise introduced by the first quantizer 20.
The processing stage 70 further comprises a first processing filter 74, the input of which is connected to the output of the decimation filter 72.
The first processing filter 74 is of the so-called IIR (infinite impulse response) type and is, for example, a third-order filter with bandwidth limited to the audio bandwidth, i.e., with 3-dB frequency of 20 kHz. In addition, the first processing filter 74, by filtering the samples of the decimated signal sdec(n), supplies a first filtered signal sfilt1(n) on its own output.
The processing stage 70 further comprises a second processing filter 76, the input of which is connected to the output of the first processing filter 74.
The second processing filter 76 is a high-pass filter of a type IIR, which performs the function of removing the d.c. component of the first filtered signal sfilt1(n).
In addition, the second processing filter 76 supplies a second filtered signal sfilt2(n) on its own output.
The processing stage 70 further comprises a demodulation stage 78, the input of which is connected to the output of the second processing filter 76. The demodulation stage 78 is designed to generate on its own output a (digital) modulus signal smod(n), indicating the envelope of the modulus of the second filtered signal sfilt2(n). For this purpose, the demodulation stage 78 may, for example, be formed by a so-called peak detector. Consequently, the demodulation stage 78 calculates the modulus of the samples of the second filtered signal sfilt2(n) and carries out a numeric filtering of the samples thus obtained. Without this implying any loss of generality, the filtering may be carried out so that the increases in value of the envelope of the modulus of the second filtered signal sfilt2(n) are followed rapidly by the demodulation stage 78, while the reductions in value of the envelope of the modulus of the second filtered signal sfilt2(n) are followed more slowly; in other words, the demodulation stage 78 may track the increases and reductions in the value of the envelope of the modulus of the second filtered signal sfilt2(n) with two different time constants.
An example of the modulus signal smod(n) is shown in
The processing stage 70 further comprises a comparator 80, the input of which is connected to the output of the demodulation stage 78. In addition, the comparator 80 is designed to generate on its own output a comparison signal scomp(t) of an analog type, an example of which is illustrated in
In particular, the comparator 80 compares the modulus signal smod(n) with a first threshold TH_HIGH and a second threshold TH_LOW, with TH_HIGH>TH_LOW; purely by way of example, the difference TH_HIGH-TH_LOW may, for example, be equal to 6 dBSPL.
Whenever the modulus signal smod(n) exceeds the first threshold TH_HIGH, the comparator 80 generates a rising edge of the comparison signal scomp(t), which assumes a value VH. Instead, whenever the modulus signal smod(n) drops below the second threshold TH_LOW, the comparator 80 generates a falling edge of the comparison signal scomp(t), which assumes a value VL.
The processing circuit 3 further comprises a zero-detection circuit 90 and a logic circuit 92.
The zero-detection circuit 90 has two inputs and an output; the two inputs are, respectively, connected to the outputs of the first and second amplification stages 6a, 6b, so that the zero-detection circuit 90 receives at input the first input signal sin1(t) and the second input signal sin2(t). In addition, the zero-detection circuit 90 supplies a clock signal CLK(t) on its own output.
The zero-detection circuit 90 generates a pulse of the clock signal CLK(t) whenever one between the first and second input signals sin1(t), sin2(t) crosses the respective zero value, the rising edge of this pulse being substantially concomitant with zero-crossing by the first input signal sin1(t) or the second input signal sin2(t), and thus also with the instant of zero-crossing by the first detection signal sd1(t) or by the second detection signal sd2(t), on the hypothesis of considering negligible the delays introduced by the first and second amplification stages 6a, 6b. In this connection, the adverb “substantially” refers to the hypothesis of neglecting the inevitable delays of switching of the output of the zero-detection circuit 90, due for example to the delays in the propagation of the signals within the zero-detection circuit 90 itself. Further, in general, in the present description it is assumed that the times of propagation of the signals within the digital microphone 1 are neglected.
The logic circuit 92 has a first input and a second input, connected, respectively, to the output of the comparator 80 and to the output of the zero-detection circuit 90, and an output, which is connected to the control inputs of the multiplexer 8 and of the equalizer 30. In addition, the logic circuit 92 supplies the aforementioned control signal sc(n) on its own output.
In detail, the logic circuit 92 operates as a so-called “edge-triggered D flip-flop”, where the datum is constituted by the comparison signal scomp(t) and the clock is constituted precisely by the clock signal CLK(t), so that the instant of (possible) switching of the output of the logic circuit 92 is determined by the clock signal CLK(t). For instance, without this implying any loss of generality, it is assumed that the instants of (possible) switching of the output of the logic circuit 92 substantially coincide (i.e., but for the inevitable switching delays of the output of the logic circuit 92) with the rising edges of the pulses of the clock signal CLK(t). Consequently, at each rising edge of the clock signal CLK(t), the control signal sc(n) assumes the value that the comparison signal scomp(t) has at the moment identified by this rising edge. It follows that the control signal sc(n) assumes alternatively the value VH or else the value VL.
In practice, in this embodiment, the control signal sc(n) has a rising edge or a falling edge concomitant with instants of zero-crossing by the first detection signal sd1(t) or by the second detection signal sd2(t). In addition, since one between the first and second input signals sin1(t), sin2(t) is in advance with respect to the other, zero-crossing by the signal in advance is followed in a short time by zero-crossing by the other signal; however, whereas the initial crossing may cause switching of the value of the control signal sc(n), the subsequent crossing does not cause any switching of the value of the control signal sc(n), since, between the initial crossing and the next crossing, there does not occur any switching of the value of the comparison signal scomp(t). It should further be noted that, for simplicity, in
This having been said, the multiplexer 8 is configured so that:
In addition, the equalizer 30 is configured so that:
In practice, the equalizer 30 varies the coefficient used by it at the same instants in which the multiplexer 8 changes the input signal, on the basis of which it generates the multiplexed signal smux(t). In addition, the equalizer 30 implements an equalization of the sensitivity-gain products regarding the first and second sensing structures 2a, 2b. In addition, the first PDM signal sPDM1(n) is formed, at each instant, on the basis of the detection signal supplied by the most appropriate sensing structure, i.e., the sensing structure that is not in saturation and that has the highest sensitivity-gain product possible, compatibly with the sound-pressure level of the acoustic signal. In addition, since the equalizer 30 switches between the first and second coefficients DIV1, DIV2 substantially at the zeros of the acoustic signal, the distortions introduced by this switching on the signals downstream of the equalizer 30 are limited.
As illustrated in
As illustrated in
The electronic device 100 is, for example, a mobile communication device, such as a cellphone, a personal digital assistant, a notebook, but also a voice recorder, a reader of audio files with voice-recording capacity, etc. Alternatively, the electronic device 100 may be a hydrophone, capable of working under water, or else a hearing-aid device.
The electronic device 100 comprises a microprocessor 101, a device memory 102, connected to the microprocessor 101, and an input/output interface 103, which is for example formed by a keypad and a screen and is also connected to the microprocessor 101.
The digital microphone 1 communicates with the microprocessor 101; in particular, the processing circuit 3 sends the aforementioned second PDM signal sPDM2(n) to the microprocessor 101, possibly after prior further processing by an electronic interface circuit (not illustrated).
The electronic device 100 further comprises a speaker 106, which is connected to the microprocessor 101 and is designed to generate sounds on an audio output (not illustrated) of the electronic device 100. In addition, the digital microphone 1, the microprocessor 101, the device memory 102, the input/output interface 103, and the speaker 106 are mounted, for example, on a single printed circuit board (PCB) 108, for instance with the surface-mount technique.
The vibrating membrane 312 includes two vibrating portions, and in particular a first portion 340 and a second portion 342. The first and second portions may represent the first and second sensing structures 2a, 2b of
The slit 356 between the main membrane 322 and the peripheral membrane 324 does not physically separate the first portion 340 in a complete way from the second portion 342, but leaves a connection in points 354. In this embodiment, the slit 356 has a rectilinear central region and curved external portions. The external portions bend, moving away from the center of the main membrane 322, towards the peripheral membrane 324. The partial separation of the main membrane 322 and of the peripheral membrane 324 enables simplification of the manufacturing process so that the vibrating membrane 312 is formed as a single layer of material in which the slit 356 is subsequently formed. In any case possible are embodiments in which the main membrane 322 and the peripheral membrane 324 are completely separated from one another, i.e., embodiments in which the slit 356 extends as far as the edges of the vibrating membrane 312.
As mentioned previously, the vibrating membrane 312 includes a plurality of anchorages 51a, i.e., of fixed portions, which are arranged at the ends of corresponding extended portions 350. The peripheral membrane 324 is fixed to anchorage regions 336 in respective edge portions 352 arranged on the bottom and top sides. The extended portions 350 extend from four corners of the main membrane 322. Each extended portion 350 has a constant width and a rounded end. The two anchorages 51a closest to the peripheral portion 324 join to the edge portions 352 in the points 354. In addition, the slit 356 separates the extended portions 350 from the edge portions 352 in the proximity of the points 354. In the embodiment illustrated in
The vibrating membrane 312 is configured so that the ratio of the area of the anchorages 51a of the main membrane 322 with respect to the area of the main membrane 322 is less than the ratio of the area of the anchorage regions 336 of the peripheral membrane 324 with respect to the area of the peripheral membrane 324. Consequently, this entails that, in use, the main membrane 322 is moved further away from the peripheral membrane 324.
Since the slit 356 is formed only in a part of the vibrating membrane 312, the main membrane 322 and the peripheral membrane 324 are physically and electrically connected together. In an alternative embodiment, the slit 356 is not formed, so that the main membrane 322 and the peripheral membrane 324 are adjacent to one another and, consequently, the displacement of the main membrane 322 and the displacement of the peripheral membrane 324 affect one another. On the opposite side, in this embodiment, since the slit 356 is present, the main membrane 322 and the peripheral membrane 324 are separated from one another, determining a more significant difference between the displacements of the main membrane 322 and of the peripheral membrane 324.
The protective membrane 317 includes a first fixed electrode 314, arranged on top of the main membrane 322, and is configured to form a capacitor with the main membrane 322. The protective membrane 317 further includes a second fixed electrode 316, arranged on top of the peripheral membrane 324, and is configured to form a capacitor with the peripheral membrane 324. The protective membrane 317 provides support for the first and second fixed electrodes 314, 316, which may be fixed to a surface of the protective membrane 317 that is located in front of the vibrating membrane 312. The protective membrane 317 may be solid, i.e., without holes. Alternatively, the protective membrane 317 may have numerous openings, configured to enable release etching during the manufacturing process, which may also provide outlets for passage of air during operation.
The protective membrane 317 further includes an insulation bridge 323 positioned between the first fixed electrode 314 and the second fixed electrode 316. The insulation bridge 323 is made of a dielectric material and is arranged over the slit 356 between the main membrane 322 and the peripheral membrane 324.
Illustrated in
The protective membrane 317 may be arranged at a single potential, or else the first and second fixed electrodes 314, 316 may be set at different potentials. Each one of the first and second fixed electrodes 314, 316 has its own separate electrical connections to respective contact pads 360, 364 (see grooves 314a, 316a that extend from the first and second fixed electrodes 314, 316). As illustrated in the subsequent figures, an ASIC or an electronic circuit may be coupled to the contact pads 360, 364.
The package 600 includes a housing 602, which forms an internal chamber 605. Within the internal chamber 605, the ASIC 604 is adjacent to the MEMS die 606. The MEMS die 606 is aligned with an opening 608 formed in the housing 602. The opening 608 is configured to enable the sound waves to enter a rear chamber 610 of the MEMS die 606 so that the vibrating membrane (not illustrated) may detect the sound waves. The ASIC 604 is configured to contain the processing circuit 3 illustrated in
The MEMS die 606 includes a protective membrane (here designated by 612), arranged on a substrate (here designated by 614). Numerous contact pads 616 are formed on the substrate 614, around the edges of the protective membrane 612. The ASIC 604 includes a plurality of respective contact pads 618, arranged on a top surface thereof. Some of the contact pads 616 are coupled to some of the contact pads 618 by wires 620. Other contact pads 622 may be formed on a top surface of the housing 602. Other contact pads 618 of the ASIC 604 are coupled to the contact pads 622 of the housing 602 and provide an electrical connection to external components, such as for example a PCB in a cellphone.
In
The MEMS die 606 is coupled to the ASIC 604 through a wire 620 that extends over a top part of the protective membrane 612. The wire 620 is arranged so as not to affect detection of the sound waves. For instance, the wire 620 may extend around an outer edge of the protective membrane 612.
The PCB 640 may be configured to house additional packages, containing for example additional processing circuits to be included in a mobile device. The additional packages may be coupled electrically to the package 600 through electrical connections in the PCB 640.
The package 600 illustrated in
Irrespective of the details regarding the package, the MEMS die 606 may have an input pin, configured to receive a signal from the processing circuit, for selecting a normal channel, a high channel, or a combination of the normal channel and of the high channel. The normal channel may be the output of the main membrane, whereas the high channel may be the output of the peripheral membrane. The MEMS die 606 may likewise have an output pin, configured to output of the normal channel, of the high channel or of the combination of the normal channel and of the high channel, as a function of the signal received on the input pin.
The signal received on the input pin may be a selected sequence, which identifies in time which signal is supplied on the output pin. For instance, the normal channel may be supplied at output if the signal on the input pin is high and remains high for a selected period of time, the high channel may be supplied at output if the signal on the input pin is low and remains low for the period of time selected, and the combined signal may be supplied at output if the signal on the input pin alternates between a high value and a low value for the period of time selected. In addition, the signal received on the input pin for selecting the combined channel may be a sequence of high values and low values, which indicates the desired ratio between the normal channel and the high channel. For instance, if the signal received on the input pin is made up of eight bits and contains more “1s” than “0s”, the output signal is based more upon the normal channel than upon the high channel. Instead, if the signal received on the input pin contains more “0s” than “1s”, the output signal is based more upon the high channel than upon the normal channel. The specific ratio between normal channel and high channel may be set by selecting the number and order of the “1s” and “0s”.
If the processing circuit is in a separate package, the selection signal, i.e., the signal present on the input pin, may be transferred onto the same input pin through an electrical connector and thus through the housing 602 as far as the MEMS die 606.
It is further possible for the MEMS die 606 to form one or more additional electronic circuits, designed to combine the high channel and the normal channel.
If the processing circuit is in the same package as the MEMS die 606, the selection signal may pass through the housing 602 as far as the MEMS die 606, or else through a wire arranged between the ASIC 604 and the MEMS die 606.
From what has been described and illustrated previously, the advantages that the present solution affords are evident.
In particular, the present processing circuit enables formation of a single stream of samples, based in each moment upon a signal coming from the sensing structure most suited to detecting the acoustic signal that impinges upon the microphone. In addition, the use of filters is limited to the processing stage 70, but for the first input filter 12 of the first sigma-delta converter 10; thus, it is limited to the portion of measurement of the sound-pressure level of the acoustic signal; consequently, as regards formation of the second PDM signal sPDM2(n), the integrity thereof is preserved, and further no delay is introduced.
In addition, the detection of zero-crossing is carried out in the analog domain, with consequent optimization of the reaction times. Once again, the adoption of a mechanism of comparison with two thresholds enables implementation of a sort of hysteresis; in fact, the comparator 80 is configured to vary the value of the comparison signal scomp(t) on the basis of the evolution in time of the modulus signal smod(n) along a curve with hysteresis. In this way, occurrence of excessively frequent switchings between the first and second coefficients DIV1, DIV2 is prevented, with consequent reduction of the distortions.
In conclusion, it is clear that modifications and variations may be made to what has been described and illustrated herein.
For instance, the digital microphone 1 may comprise, in addition to the first and second sensing structures 2a, 2b, one or more additional sensing structures, each of which is associated to a corresponding coefficient, which may be used by the equalizer 30 for multiplying the samples of the first encoded signal scode1 (n). In this case, the comparator 80 implements a scheme of comparison with more than two thresholds, for example with hysteresis. Consequently, the comparison signal scomp(t), as on the other hand also the control signal sc(n), may assume more than two values. As a result, the logic circuit 92 is a logic circuit designed to process signals with more than two levels and may include, amongst other things, a sample-and-hold and an analog-to-digital converter. In particular, assuming that the thresholds are in a number equal to N and comprise a minimum threshold and a maximum threshold, N+1 ranges of values are obtained, which include a bottom range, delimited at the top by the minimum threshold, a top range, delimited at the bottom by the maximum threshold, and a number greater than or equal to zero of intermediate ranges; this having been said, the comparator 80 operates so that:
Instead of the first and second sigma-delta converters 10, 40 converters of a different type may be present. For instance, the first sigma-delta converter 10 may be replaced by a multilevel analog-to-digital converter, or else by a sigma-delta converter including a quantizer having more than two quantization levels, and thus more than one threshold. In this case, the encoder 28 may be absent, and further, instead of the first PDM signal sPDM1(n), a stream of samples is generated, each of which is encoded on more than one bit.
In this connection, all the multibit signals generated by the processing circuit 3, such as for example the first and second encoded signals scode1(n), scode2(n), may be encoded in binary form with an encoding different from the one described. It is thus possible for the samples of the first and second encoded signals scode1(n), scode2(n) to be encoded with encodings different from the two's complement, such as for example a pure binary encoding, or else an unsigned encoding. It is likewise possible that at least part of the connections present between the blocks of the processing circuit 3 is of a type different from the one described; for example, in the digital domain, it is possible to adopt serial connections, instead of connections of a parallel type.
It is further possible for the waveform of the clock signal CLK(t) to be different from what has been described; for example, it is possible for the zero-detection circuit 90 to generate a rising edge of the clock signal CLK(t) whenever one between the first input signal sin1(t) and the second input signal sin2(t) crosses the zero and for it to generate a falling edge of the clock signal CLK(t) whenever the other between the first and second input signals sin1(t), sin2(t) crosses zero. Likewise, as mentioned previously, it is possible for the clock signal CLK(t) to indicate the zero-crossings of just one between the first and second input signals sin1(t), sin2(t). Once again, the clock signal CLK(t) may have rising edges that are not substantially concomitant with the instants of zero-crossing of the first and second input signals sin1(t), sin2(t); for example, for each pair of corresponding zeros (i.e., ones originating from the same instantaneous value of the acoustic signal and offset in time on account of the different delays introduced by the first and second sensing structures 2a, 2b, as well as by the first and second amplification stages 6a, 6b) of the first and second input signals sin1(t), sin2(t), it is possible for the clock signal CLK(t) to have a rising edge that falls between the instants of this pair of corresponding zeros.
Likewise possible are embodiments in which the zero-detection circuit 90 is implemented so that, in the case where, during a time interval of predetermined duration, there is no zero-crossing by either the first input signal sin1(t) or the second input signal sin2(t), it generates in any case a pulse of the clock signal CLK(t). In this way, the control signal sc(n) is updated also in the case where, for example, the acoustic signal ceases completely, but, on account of the presence of offset, following upon cessation of the acoustic signal there is in any case no zero-crossing by either the first input signal sin1(t) or the second input signal sin2(t); in this way, for practical purposes a sort of reset of the processing circuit 3 is obtained.
As regards operation of the logic circuit 92, the instants of (possible) switching of the output may be determined in a way different from what has been described; for example, these instants may coincide with the instants in which the falling edges of the clock signal CLK(t) occur.
As regards the second sigma-delta converter 40, it may be absent, in which case the processing circuit 3 supplies at output a multibit signal.
Once again, it is possible for the first and second amplification stages 6a, 6b to be absent, and thus that G1=G2=1. In other words, the first and second input signals sin1(t), sin2(t) may be, respectively, equal to the first and second detection signals sd1(t), sd2(t).
Finally, even though in the present description, in order to indicate the operation performed by the equalizer 30, reference has been made to the division, this operation may likewise be a multiplication by a factor alternatively equal to the first coefficient DIV1 or else the second coefficient DIV2; in this connection, is further possible for one or both of the first and second coefficients DIV1, DIV2 to be greater than unity.
The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
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