PROCESSING METHOD FOR PROVIDING, STARTING FROM SIGNALS ACQUIRED BY A SET OF SENSORS, AN AGGREGATE SIGNAL AND DATA ACQUISITION SYSTEM USING SUCH METHOD

Abstract

Embodiment for forming an aggregate signal from a plurality of starting signals, comprising: acquiring said starting signals through respective sensors of a homogeneous sensors group;converting acquired signals in respective digital signals having data represented with a predetermined bits number;processing the digital signals to form aggregate signal.

Description

PRIORITY CLAIM

This application claims priority from European patent application No. 06425259.6, filed Apr. 12, 2006, which is incorporated herein by reference.

TECHNICAL FIELD

An embodiment of the present invention relates to data acquisition, processing, and transmission, and in particular is concerned with a processing method for providing an aggregate signal, starting from signals acquired from a set of sensors. An embodiment of the present invention further relates to a data-acquisition system using such method.

BACKGROUND

As it is known, in an ever increasing number of applications is the widespread use of sensors networks for acquiring various kind of data and for transmitting such data to a remote processing unit. Just to mention a few examples, the use of sensor networks has proven itself particularly advantageous in the security-systems field, in bio-medical applications, in the environment-control field, and in the transport field. In many applications, the sensor networks used are wireless networks, often referred to by the WSN acronym (Wireless Sensors Network).

It is known that in sensor networks, primarily in wireless networks, reducing the area or volume occupied by circuits or components included in the sensors is often a system requirement. For instance, presently in sensor wireless networks are generally used micro-sensors, or MEMS (an acronym of the expression Micro Electro-Mechanical Sensors), realized by CMOS technology, and in the future one envisages a use of sensors realized by sub-micrometric sophisticated technology CMOS (DSM CMOS).

In sensor networks, primarily in wireless networks, another system restraint is a low-energy consumption of the various system components supplied by a battery, with the purpose to maximize the battery life.

In sensor networks, and particularly in wireless networks, to limit the energy required to transmit the sensor output via signals to the remote processing unit, a transmission technique is known, that envisages grouping the sensors provided for acquiring data concerning homogeneous quantities, in such a way as to form groups of sensors. Each of such groups is associated with a local processing unit (that, generally, may be integrated in a sensor of the group), provided for receiving signals output by the sensors, processing such signals to form an aggregate signal, and transmitting such aggregate signal to the remote processing unit. The local processing unit generally comprises a micro-controller with very low power dissipation (MCU, Ultra-low-power Micro Controller) adapted to execute the above described operations.

A specific example of the above indicated transmission technique is disclosed in a paper by A. Wang, W. Einzelam and A. P. Chandrakasan entitled “Energy Scalable Protocols for Battery-Operated MicroSensor network” Kluwer Journal of VLSI Signal Processing, pp. 223-239, November 2001, which is incorporated by reference.

In the above-described transmission technique, the aggregate signal is obtained from the local processing unit by a merge (also referred to in the field by the word “beamforming”) of signals output by various sensors of the group, exploiting the redundancy present in such signals. In the above cited paper, such merge is obtained by adaptive equalization. In other techniques, the merge is obtained by a Kalman filtering.

The above-described beamforming techniques require the local processing unit to perform computations of significant complexity, such as for instance arithmetic operations in fixed or floating point. This implies a sizeable power consumption in the local processing unit, which, in practice, is forced to operate as a digital signal processor (DSP).

SUMMARY

An embodiment of the present invention makes available a signal processing method, or a beamforming method, for provide an aggregate signal from a plurality of starting signals and that overcomes one or more of the above-described shortcomings.

BRIEF DESCRIPTION OF THE DRAWINGS

Features and advantages of one or more embodiments of the present invention will be better understood from the following detailed description, given by way of example, and, therefore, in no way limiting in relation to the appended figures.

FIG. 1 shows an exemplary block diagram of a data-acquisition system according to an embodiment of the present invention, comprising a sensors network, a local processing unit and a remote processing unit.

FIG. 2 shows an exemplary block diagram of the local processing unit of FIG. 1.

FIG. 3 shows an exemplary logic scheme of a swap module of the local processing unit of FIG. 2.

FIG. 4 shows an exemplary block diagram of the remote processing unit of FIG. 1.

FIG. 5 shows a waveform portion of an exemplary output signal provided by a sensor and a waveform portion of a signal extracted from the aggregate signal.

FIGS. 6 and 7 each show a waveform section of an exemplary output signal provided by a sensor and a waveform section of the signal extracted from the aggregate signal following a filtering operation.

FIG. 8 shows waveforms of exemplary output signals provided by a group of four sensors and corresponding signals extracted from an aggregate signal y_beam.

In the figures, same or similar elements are indicated with the same reference numerals.

DETAILED DESCRIPTION

In FIG. 1 is schematically shown an example of a data acquisition system, generally indicated at 1, comprising a sensor network 2, a local processing unit L_PU and a remote processing unit R_PU.

Sensor network 2 comprises a plurality of sensors U₁, . . . , U₅, for instance micro-sensors (MEMS), that together forms a set of homogeneous sensors U₁, . . . , U₅. In this description, the term “homogeneous group” of sensors U₁, . . . , U₅ means a group of sensors adapted to measure the same physical quantity to provide in output a respective acquired signal x₁, . . . , x₅ representing such physical quantity. For instance sensors U₁, . . . , U₅ might all be sensors adapted to measure a respective value of room temperature. In another example, sensors U₁, . . . , U₅ might all be sensors adapted to measure a respective value of a same chemical quantity.

Although in FIG. 1 a sensor network 2 has been schematically shown comprising five sensors U₁, . . . , U₅, the network 2 may include any integer number of sensors at least equal to two.

Each sensor U₁, . . . , U₅ comprises one or more transducers for acquiring signals x₁, . . . , x₅, representative of the measured physical quantity, and comprises further resources for generating and transmitting such signal x₁, . . . , x₅ processing and output transmission. More specifically, each sensor U₁, . . . , U₅ comprises analog/digital conversion means, to provide in output said signals x₁, . . . , x₅ as digital signals, that is comprising data in a digital format and having a resolution of N_res bits. Hereinafter, it is assumed, without necessarily introducing any limitation, to the case wherein signals x₁, . . . , x₅ output from sensors U₁, . . . , U₅ are digital signals, having for instance data represented on N_res=16 bits.

In one alternative embodiment signals x₁, . . . , x₅ output from sensors network 2 are analog signals destined to be converted in digital signals by suitable analog/digital conversion means provided in the local processing unit L_PU.

Sensors network 2 comprises a local processing unit L_PU which preferably, as in the example illustrated in FIG. 1, is integrated in one of said network 2 sensors, in the shown example in sensor U₅. In an alternative embodiment, but operatively equivalent, local processing unit L_PU could be separate from each of the sensors U₁, . . . , U₅ of the sensors network 2.

Local processing unit L_PU is such to receive different digital signals, x₅ acquired and provided in output from network 2 sensors U₁, . . . , U₅.

Local processing unit L_PU comprises processing means for processing digital signals x₁, . . . , x₅ provided from sensors U₁, . . . , U₅ and to form, starting from such signals, an aggregate digital signal y_beam to be transmitted to the remote processing unit R_PU. Local processing unit L_PU comprises processing means in the form of a low-dissipation micro-controller.

In an embodiment, sensor network 2, and more generally data-acquisition system 1, is of a wireless type. In this case, in practice, data transmission among different entities constituting network 2, or more generally data-acquisition system 1, takes place by free space propagation of radio frequency signals. In alternative embodiments, such transmission might take place via wired connections between at least some of different network/system entities. For instance, there may be proposed wired connections between sensors U₁, . . . , U₄ and sensor U₅, or more generally between each sensor network 2 sensors U₁, . . . , U₅ and a the local processing unit L_PU.

For the digital signals x₁, . . . , x₅ transmission to local processing unit L_PU, it is possible to envisage various types of access modes. For instance, it is possible for such transmission to envisage for each signal x₁, . . . , x₅ a dedicated frequency channel (FDMA) or as, an alternative, envisage a time-sharing multiple access (TDMA) of different signals x₁, . . . , x₅ to a single channel (TDMA), or even envisage a mixed system FDMA/TDMA.

In FIG. 2 is shown a block diagram of an embodiment of local processing unit L_PU, in this example integrated in one of the homogeneous sensors U₁, . . . , U₅ set. Local processing unit L_PU is such to receive input digital signals x₁, . . . , x₅ provided from the sensors and comprises processing means B_swap, B_form for forming an aggregate signal Y_beam.

Processing means B_swap, B_form comprise a swap block B_swap adapted to modify signals x₁, . . . , x₅ received in input exchanging the data format of each of said signals from a first format to a second format. In FIG. 2 by x₁(t), . . . , x₅(t) are indicated at clock cycle t digital data in the first format of signals x₁, . . . , x₅ and by xs₁(t), . . . , xs₅(t) are indicated at clock cycle t digital data in the second format of signals xs₁, . . . , xs₅.

Each data xs₁(t), . . . , xs₅(t) in the second format is obtained from a respective data in the first format x₁(t), . . . , x₅(t) by a permutation operation such as to change the bit positions within each data based upon a permutation scheme p₁(t), . . . , p₅(t) associated with data x₁(t), . . . , x₅(t) and with the specific digital signal x_i, . . . , x₅ comprising such data x_i(t), . . . , x₅(t).

As may be noted by a coordinated observation of FIGS. 1 and 2, in an embodiment, the permutation schemes p₁(t), . . . , p₅(t) may be selected by the remote processing unit R_PU and transmitted to the local processing unit L_PU trough at least one signal P.

For example, the swap block B_swap has been shown as formed by a plurality of swap modules B_s1, B_s2, B_s3, B_s4, B_s5, each assigned to process a respective input signal x_i, . . . , x₅. In an alternative embodiment, swap block B_swap may be implemented through a single processing unit shared among all signals x₁, . . . , x₅.

In FIG. 3 is shown an example of the logic scheme of a swap module, and particularly of swap module B_s1 provided for processing signal x_i. For illustration simplification only, the input data x₁(t) (or first format data) at clock cycle t is represented as data having a resolution equal to N_res=4 bits. Owing to the fact that swap module B_s1 is such as to perform only a position swap, or permutation, of the input data bits (first format data) also output data xs₁(t) (second format data) from swap module B_s1 will be represented in this example as a data having a resolution equal to N_res=4 bits.

In general, if digital signals x_i-x_n data input to the swap module are each represented by N_res=2ⁿ bits, the permutation scheme (indicated as p_i in FIG. 3) may be in turn expressed as a data, or a coded word, that may take up to N_res! values, each may be represented with N_res digits, or each may be represented with n bits.

In the example shown in FIG. 3, at the clock cycle t input data is x₁(t)=0110 while output data is xs₁(t)=1001. In such instance the permutation scheme (referred to the input and output positions numbered as 0, 1, 2, 3) has the expression 2-3-0-1.

In practice, if the permutation scheme is expressed as 2-3-0-1, this is equal to say that swap module B_s1 performs a bit permutation such that:

the bit having position 0 in the input data has position 2 bit in the output data;

the bit having position 1 in the input data has position 3 bit in the output data;

the bit having position 2 in the input data has position 0 bit in the output data; and

the bit having position 3 in the input data has position 1 bit in the output data;

In more general terms, a swap module B_s1 equals functionally a combinatory logic operator S (or swap operator) for which is valid a relation of type:

B _s1(t)=S[x₁(t), p₁(t)]=Xs₁(t).  (1)

A property of such swap operator S is that the operator is reversible, therefore the reverse operator S⁻¹ exists such that x₁(t)=S⁻¹[xs₁(t), p₁(t)]. Further, direct and reverse swap operations may be carried out using the same S operator, applying two distinct permutation schemes (direct p₁(t) and reverse p⁻¹(t)) linked to each other by the bi-univocal relationship:

x ₁(t)=S⁻¹[xs₁(t), p₁(t)]=S[xs₁(t), p⁻¹(t)].  (2)

A few examples of permutation scheme p¹ and related reverse schemes p⁻¹ are shown in the following table:

p1         p−1
1, 2, 3, 0 3, 0, 1, 2
1, 0, 2, 3 1, 0, 2, 3
2, 1, 3, 0 3, 1, 0, 2
1, 3, 0, 2 2, 0, 3, 1

In general, using a swap operator S for digital data transformation from a first to a second format is known. For instance, applying swap operators to digital data, in the specific field of data transmissions, and more particularly with the aim of reducing a bus switching activity, is described in the US patent application 2004/0201505 A1, which is incorporated by reference.

Another property of a swap operator S resides in the fact that given a positional bitwise logic operator O_pl[d1(t),d2(t)], wherein d1(t) and d2(t) are data each represented on N_res bits, the following property is valid:

S[O _pl [d1(t),d2(t)],p(t)]]=

=O_pl[S[d1(t),p(t)],S[d2(t),p(t)]],  (3)

wherein p(t) represents any swap sequence.

For instance, in case the positional bitwise logic operator O_pl is the EX-OR operator, represented by ⊕, the above property translates itself in:

S[d1(t)⊕d2(t)],p(t)]]=

=S[d1(t),p(t)]⊕S[d2(t),p(t)].  (4)

wherein p(t) represents any swap sequence.

Other examples of positional bitwise logic operators are the following: AND, NAND, OR, NOR, EX-NOR, etc. . . . or any combination of said operators.

In case, as often occurs, input signal data x₁, . . . , x₅ to be modified from the swap block B_swap, and, more particularly, swap units B_s1, B_s2, B_s3, B_s4, B_s5, are represented by a considerable number of bits (for instance 16), one may realize the swap operation such that it operates rigidly on M blocks of input data bits, wherein M is a greater than 1 integer, overall such as envisaged from the teachings of the above mentioned US patent application 2004/0201505 A1. This allows, as will be explained better in the following, a reduction in the permutation schemes' p₁(t), . . . , p₅(t) length, and in the number of trials to be performed at the remote processing unit R_PU in the permutation schemes p₁(t), . . . , p₅(t) research operations. This is due to the fact that, as described in the abovementioned US patent application, in the case wherein the permutation schemes operate on single bits of the data to be processed having a resolution of N_res bits, any permutation schemes may be selected within a set of N_res! (factorial) possible permutation schemes, while in the case wherein one operates upon M groups of bits this may be selected among M! (factorial) possible permutation schemes. This allows one to reduce considerably computational complexity at the remote processing unit R_PU of the permutation schemes to be utilized by the local processing unit.

In an embodiment, if each of the input signals to the swap block B_swap shows stationarity characteristics (for example strict stationarity), it is possible to envisage for each x₁, . . . , x₅ input signal a dedicated permutation scheme group (or set) comprising a finite number W of permutation schemes to be utilized cyclically (i.e., repeatedly), for instance sequentially, for modifying the data format of said input signal. Further, in case x₁, . . . , x₅ input signals present modest stationarity characteristics, it is possible to envisage for each said x₁, . . . , x₅ signals an update of said sets of permutation schemes by the remote processing unit R_PU with an update frequency, for example, much lower compared to the clock frequency of signals x₁, . . . , x₅ received in input to the swap block B_swap.

Referring to FIG. 2, processing means B_swap and B_form of local processing unit L_PU further comprise an aggregation (beamforming) block B_form for producing starting from signals xs₁(t), . . . , xs₅(t) as processed by swap block B_swap an aggregate signal y_peam (t) having N_res bits resolution data.

Aggregation block B_form produces such aggregate signal y_beam by applying a positional logic operator bitwise O_pl upon corresponding bits of signals xs₁(t), . . . , xs₅(t) for producing a single bit of the aggregate signal y_beam. In other words, for each, N_res bits, data xs₁(t), . . . , xs₅(t) of input signals xs₁, . . . , xs₅, beamforming block B_form provides in output an aggregate signal y_beam data y_beam(t) having a N_res bits resolution and such that:

y _beam(t)=O_pl[xs₁(t), . . . , xs₅(t)].  (5).

In an embodiment, the positional logic operator O_pl is the Boolean operator EX-OR (also called exclusive OR, also represented by symbol ⊕).

Only to make an example in this case, named xs₁(t)(i), xs₂(t)(i), xs₃(t)(i), xs₄(t)(i) xs₅(t)(i) the i-th bits (with i comprised between 0 and N_res−1) of signals xs₁, . . . , xs₅ at clock cycle t, aggregation block B_form produces the i-th bit of aggregate signal y_beam (t) at clock cycle t by computing:

$\begin{array}{cc}\begin{array}{c}{y}_{\mathrm{beam}}\left(t\right)\left(i\right)={\mathrm{xs}}_1\left(t\right)\left(i\right)\oplus {\mathrm{xs}}_2\left(t\right)\left(i\right)\oplus {\mathrm{xs}}_3\left(t\right)\left(i\right)\oplus {\mathrm{xs}}_4\left(t\right)\left(i\right)\oplus {\mathrm{xs}}_5\left(t\right)\left(i\right)\\ =\sum _{\oplus }^u{\mathrm{xs}}_u\left(t\right)\left(i\right)\end{array}& \left(6\right)\\ \mathrm{for}u=1,\dots ,5.& \end{array}$

Expressing a previous relationship as a function of the signals x₁(t), . . . , x₅(t) received in input from local processing unit L_PU and clearing index i, the aggregate signal y_beam(t) data at clock cycle t maybe written in the form:

$\begin{array}{cc}{y}_{\mathrm{beam}}\left(t\right)=\sum _{\oplus }^uS\left[x_u\left(t\right),p_u\left(t\right)\right]& \left(7\right)\end{array}$

wherein p_u(t) is the permutation scheme assigned at clock cycle t to digital signal x_u(t) to modify said data format through swap block B_swap. As previously explained, permutation schemes p_u(t) that represent in practice digital signatures for the same signal x_u may be repeated cyclically as clock t cycles vary. In that way, permutation sequences p_u(t) may be used to apply to the same signal from a set (associated with said signal) comprising a finite number W of possible sequences identified by the remote processing unit R_PU to modify, in practice to “sign”, said signal. More generally, using a bitwise positional logic operator O_pl in the aggregation block B_form one has:

$\begin{array}{cc}{y}_{\mathrm{beam}}\left(t\right)=\sum _{O_{\mathrm{pl}}}^uS\left[x_u\left(t\right),p_u\left(t\right)\right].& \left(8\right)\end{array}$

Referring to FIG. 1, in an embodiment, local processing unit L_PU is such as to send aggregate signal y_beam thus obtained to remote processing unit R_PU using a digital modulation, such as for instance a QPSK modulation or a B-PSK modulation compliant with the IEEE 802.14.5 standard.

Remote processing unit R_PU is such as to receive said aggregate signal y_beam to decode it with the aim of extracting (that is detect) from it single signals x₁, . . . , x₅ supplied in output by sensors U₁, . . . , U₅ of sensors network 2, or more correctly, of extracting from y_beam an as-accurate-as-possible estimate of such x₁, . . . , x₅ signals. For purposes of the present description, an “estimate as accurate as possible” is meant an estimate having an accuracy level compatible with some predefined system requirements.

In FIG. 4 is shown an exemplary block diagram of an embodiment of a remote processing unit R_PU.

Such remote processing unit R_PU comprises a reverse swap block B_swap⁻¹ similar to the above described swap block referring to the local processing unit L_PU and to FIG. 2.

In FIG. 4 only by way of example reverse swap block B_swap⁻¹ has been represented as comprising a plurality of reverse swap blocks B_s1⁻¹, . . . , B_s5⁻¹ each provided for processing the aggregate signal y_beam for reconstructing a respective signal x₁, . . . , x₅ provided in output from sensors U₁, . . . , U₅ and transmitted to local processing unit L_PU.

In practice, reverse swap block B_swap⁻¹ operates in such a way to process the aggregate signal y_beam by applying to said signal data-swap operators that use reverse permutation schemes p₁⁻¹, . . . p₅⁻¹ with respect to permutation schemes p₁, . . . , p₅ used by swap block B_swap in local processing unit L_PU.

As an example, to extract the u-th signal from the aggregate-signal-reverse swap block B_swap⁻¹ is to execute the following swap operation:

$\begin{array}{cc}\begin{array}{c}S\left[y_{\mathrm{beam}}\left(t\right),p_u^{-1}\left(t\right)\right]=S\left[\sum _{\oplus }^uS\left[x_u\left(t\right),p_u\left(t\right)\right],p_u^{-1}\left(t\right)\right]\\ =x_u\left(t\right)\oplus \sum _{\oplus }^{m\ne u}S\left[S\left[x_m\left(t\right),p_m\left(t\right)\right],p_u^{-1}\left(t\right)\right]\\ =x_u\left(t\right)\oplus w_u\left(t\right).\end{array}& \left(9\right)\end{array}$

From the above cited relationship, which refers to the specific case wherein the positional logic operator used to form signal y_beam is the Boolean operator EX-OR, it is evident that the extracted signal has been corrupted by a noise process due to all remaining signals that have contributed to form aggregate signal y_beam at local processing unit L_PU. It is observed that the above-cited relationship as an example for the specific case of EX-OR operator may also be true for other bitwise positional logic operators.

For this reason, the remote processing unit R_PU comprises a search block P_search provided for searching permutation schemes, or better sets (or sequences) comprising a limited and restricted number W of permutation schemes, to be transmitted to the local processing unit L_PU with the aim of reducing as far as possible, from each u-th signal to be extracted (i.e., to be revealed) from aggregate signal y_beam, the interference due to the process w_u(t).

This in practice reduces itself to the search of permutation scheme sets such as to satisfy the following relationship:

$\begin{array}{cc}{w}_u\left(t\right)=\sum _{\oplus }^{m\ne u}S\left[S\left[x_m\left(t\right),p_m\left(t\right)\right],p_u^{-1}\left(t\right)\right]\le \varepsilon & \left(10\right)\end{array}$

wherein ε is an arbitrary small predefined value. The above criteria correspond to minimize noise energy E_u due to w_u(t) process. Such energy E_u is given by:

$\begin{array}{cc}{E}_u=\sum _{i=0}^{N_{\mathrm{res}}-1}{w_u\left(t\right)\left(i\right)}^2·2^{2·i},& \left(11\right)\end{array}$

wherein w_u(t)(0) is the signal w_u(t) least-significant bit while w_u(t)(N_res−1) is the signal w_u(t) most-significant bit.

The search of the U permutation sequences sets (each sequence comprising W permutation schemes) according to the above-noted criteria has a computational complexity such as (N_res!)^U·W, wherein U is the number of signals (in this example, U=5) that contribute to the y_beam aggregate-signal formation. This applies in the case wherein the permutation schemes operate independently on each bit of the data signals provided in output from the sensors.

In the case in which instead the permutation schemes are such as to operate upon M bit sets of the data signals provided in output from the sensors, the U permutation sequences sets search according to above-noted criteria has a computational complexity that reduces itself to (M!)^U·W.

In a first embodiment, the permutation schemes sequences search problem may be solved in a heuristic way, through the study of the characteristics of the signals provided in output from sensors U₁, . . . , U₅ such as to minimize the noise spectral density of w_u(n). A shortcoming of this methodology is given from the high computational complexity and from the requested times to execute such heuristic search.

In an alternative embodiment, search block P_search executes the permutation-sequence-schemes search operation in a sub-optimal way minimizing (or maximizing) a predefined cost function, that represents the search operation metric and that is given by the sum (or by the product, using logarithms) of an individual contribution plurality. In that case, in an embodiment, search block P_search operates according to a Viterbi algorithm.

As it is known, such algorithm application, that represents a “brick” of telecommunications theory, is not limited to signals decoding and equalization, because such algorithm more generally represents a strategy to minimize (or maximize) a cost function based upon a system description in terms of inputs, states and outputs. Such system description is known in the field by the name of “trellis diagram”.

In an embodiment, search block P_search realizes a Viterbi algorithm according to the following operations:

a) casually generate a permutation schemes sequence (in practice, comprising W schemes) to be associated with first x₁ of U signals provided in output from sensors, and

For remaining U−1 signals x₂, . . . , x₅:

b) identify, operating signal by signal and through trials, respective permutation schemes sequences, such as to minimize for each (remaining) signal x_u a given cost function (or metric) of energy E_u (substantially as defined in formula 10) of interference (substantially as defined in formula 9) of the other signals whose permutation schemes have already been identified through Viterbi algorithm.

In this way “almost-orthogonal” permutation sequences schemes are obtained, that is permutation sequences schemes such to render, for each signal extracted from aggregate signal y_beam, the interference contribution at formula 10 as small as possible.

An embodiment of a Viterbi algorithm carried out by search block P_search uses a fully connected trellis diagram. This means that in the Viterbi algorithm, once a selected permutation scheme (start state) starts at cycle t−1, it is possible to carry out a transition (that is carry out a trial) at cycle t towards any permutation scheme (arrival state) including the start one. This selection, compared to the use of a partially connected trellis, does not limit the system's degrees of freedom during the permutation schemes sets search. On the contrary, adopting a partially connected trellis scheme may be a strategy to be used to reduce the number of trials to be carried out during the permutation schemes sequence.

A Viterbi algorithm of depth D (D is a parameter whose meaning is known to a person skilled in the art), is significantly less with respect to a number of sequences W that are part of a same set of permutation sequences (e.g.: W=32 and D=16).

In an embodiment, remote processing unit R_PU, besides the search operations of permutation schemes sequences and of extraction of different signals from the aggregate signal, carries out post-processing operations on extracted signals. In fact, extracted signals from aggregate signal y_beam may show replicas in the time domain (due to frequency domain sampling) and high-frequency components that require a base-band conversion and a subsequent low-pass-type filtering. Such filtering may be carried out by a Butterworth filter or an elliptic type filter (not shown in FIG. 4 scheme).

Experimental tests and simulations have demonstrated the effectiveness, in terms of power savings at the remote processing unit, as compared to known art methods.

In FIG. 5 is shown the time pattern of a signal provided in output by one of the sensors (indicated as x-Tx) and of the corresponding signal (indicated as x_Rx) extracted by the remote processing unit R_PU from the aggregate signal. In this case, the transmitted signal is an absolute value sinusoidal waveform, while the number U of signals that have contributed to signal aggregated y_beam is equal to 4 (in practice, U=4). As may be noticed in FIG. 5, extracted signal x_Rx shows high frequency components.

In the graph of FIG. 6, signal x_Tx is compared with extracted signal x_Rx following a filtering operation by an 8-pole low-pass Butterworth filter with a normalized frequency of 0.000025 Hz.

In the graph of FIG. 7, transmitted signal x_Tx is compared with extracted signal x_Rx after a filtering operation by an elliptic two-pole low-pass filter having a normalized frequency equal to 0.025 Hz.

Finally, in FIG. 8 four signals are shown x₁, . . . , x₄ provided in output from four sensors U₁, . . . , U₄ (of a four-sensor group) and corresponding signals x_1—Rx, . . . , x_1—Rx extracted from aggregate signal y_beam, filtered and detected.

The sensor group 2 of FIG. 1 may be disposed on an integrated circuit (IC) that may be part of a first system and coupled to another IC such as a processor/controller. The remote processor R_PU may by formed on the same or a different IC, and this IC may be part of the first or part of a second system, and coupled to another IC such as a processor/controller.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.

Claims

1.-18. (canceled)

19. An encoder, comprising: a first node operable to receive a first digital word that includes symbols in respective symbol positions within the first word;a second node operable to receive a second digital word that includes symbols in respective symbol positions within the second word; andan aggregator circuit coupled to the first and second nodes and operable to generate an aggregate word by logically combining each symbol within the first word with a symbol in a respective position within the second word.

20. The encoder of claim 19 wherein the first and second nodes comprise a same node.

21. The encoder of claim 19 wherein: each symbol comprises a respective bit; andeach symbol position comprises a respective bit position.

22. The encoder of claim 19 wherein the aggregator circuit is operable to logically combine each symbol within the first word with a symbol in a same position within the second word.

23. The encoder of claim 19 wherein the aggregator circuit is operable to change for each symbol within the first word the respective position within the second word.

24. The encoder of claim 19 wherein the aggregator circuit is operable to change for each symbol within the first word the respective position within the second word in response to a signal from a source remote from the circuit and the first and second sensors.

25. The encoder of claim 19 wherein the aggregator circuit is further operable to: receive first and second patterns from a source remote from the aggregator circuit and the first and second sensors;change the positions of the two symbols within the first word according to the first pattern; andchange the positions of the two symbols within the second word according to the second pattern.

26. The encoder of claim 19 wherein the aggregator circuit comprises a processor.

27.-31. (canceled)

32. A system, comprising: a first device operable to generate a first digital word that includes symbols in respective symbol positions within the first word;a second device operable to generate a second digital word that includes symbols in respective symbol positions within the second word; andan aggregator circuit coupled to the first and second devices and operable to generate an aggregate word by logically combining each symbol within the first word with a symbol in a respective position within the second word.

33. The system of claim 32 wherein: the first device comprises a first sensor operable to generate the first digital word in response to a first stimulus; andthe second device comprises a second sensor operable to generate the second digital word in response to a second stimulus.

34. The system of claim 33 wherein the first stimulus is the same as the second stimulus.

35. The system of claim 33 wherein: the first sensor comprises, a first sensor element operable to generate in response to the first stimulus a first analog signal, anda first converter coupled to the first sensor element and operable to convert the first analog signal into the first digital signal; andthe second sensor comprises, a second sensor element operable to generate in response to the second stimulus a second analog signal, anda second converter coupled to the second sensor element and operable to convert the second analog signal into the second digital signal.

36. The system of claim 32 wherein the first and second devices and the aggregator circuit are disposed on a same integrated circuit.

37. The system of claim 32 wherein the first and second devices and the aggregator circuit are disposed on at least two integrated circuits.

38. The system of claim 32, further comprising a controller coupled the aggregator circuit.

39. The system of claim 32 wherein the first and second devices, the aggregator circuit, and the controller are disposed on a same integrated circuit.

40. The system of claim 32 wherein the first and second devices, the aggregator circuit, and the controller are disposed on at least two integrated circuits.

41.-43. (canceled)

44. A method, comprising: receiving a first digital word that includes symbols in respective symbol positions within the first word;receiving a second digital word that includes symbols in respective symbol positions within the second word; andgenerating an aggregate word by logically combining each symbol within the first word with a symbol in a respective position within the second word.

45. The method of claim 44 wherein generating the aggregate word comprises performing an exclusive or of each symbol within the first word with a symbol in a respective position within the second word.

46.-47. (canceled)