Processor and method for controlling processor

Abstract

A processor judges, by a comparator, match between an address determined to be a breakpoint of the CPU core and an address of a data cache at which the CPU core accesses the data cache. The data cache outputs a cache hit signal indicating a result of detection of a cache hit/miss at the time of the access. Further, an AND circuit outputs a data break signal to the CPU core, based on a match judgment signal from the comparator and the cache hit signal from the data cache, and causes the CPU core to execute a break.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic for illustrating mismatch caused when more than one core accesses an identical memory area;

FIG. 2 is a schematic of a circuit configuration of a processor according to a first embodiment of the present invention;

FIG. 3 is a schematic of a circuit configuration of a processor according to a second embodiment of the present invention;

FIG. 4 is a schematic of a circuit configuration of a processor according to a third embodiment of the present invention;

FIG. 5 is a schematic for illustrating transition of states of a data cache in a copy back mode; and

FIG. 6 is a schematic for illustrating a relation between an operation of a CPU core and contents of a main memory in the copy back mode.

Claims

1. A processor comprising: a judging unit configured to judge match between an address determined as a breakpoint of a central-processing-unit (CPU) core and an address of a cache at which the CPU core accesses the cache;a cache hit/miss detecting unit configured to detect a cache hit/miss occurred at time of access by the CPU core; anda generating unit configured to generate, based on a result of judgment by the address judgment unit and a detected cache hit/miss, a break signal to cause the CPU core to execute a break.

2. The processor according to claim 1, further comprising a setting unit configured to set a condition to cause the CPU core to execute the break, and to output a break permission signal for permitting the break to the generating unit, based on the condition and the detected cache hit/miss, wherein the generating unit is configured to generate the break signal based on the result of judgment and the break permission signal.

3. The processor according to claim 2, further comprising a state detecting unit configured to detect a state of data in the cache, the data stored corresponding to each data address, wherein the state detecting unit is configured to detect whether the state is a dirty state or a clean state, the dirty state in which the data has been rewritten by the CPU core at the time of the access, the clean state in which the data has not been rewritten, andthe setting unit is configured to output the break permission signal based on the state.

4. The processor according to claim 2, wherein the condition includes detection of a cache hit by the cache hit/miss detecting unit, andthe setting unit is configured to output the break permission signal when the cache hit/miss detecting unit detects the cache hit, and not to output the break permission signal when the cache hit/miss detecting unit detects the cache miss.

5. The processor according to claim 2, wherein the condition includes detection of a cache hit by the cache hit/miss detecting unit, andthe setting unit is configured to output the break permission signal when the cache hit/miss detecting unit detects the cache miss, and not to output the break permission signal when the cache hit/miss detecting unit detects the cache hit.

6. The processor according to claim 3, wherein the condition includes detection of the dirty state, andthe setting unit is configured to output the break permission signal when the state detecting unit detects the dirty state, and not to output the break permission signal when the state detecting unit detects the clean state.

7. The processor according to claim 3, wherein the condition includes detection of the clean state, andthe setting unit is configured to output the break permission signal when the state detecting unit detects the clean state, and not to output the break permission signal when the state detecting unit detects the dirty state.

8. The processor according to claim 2, wherein the generating unit is configured to cause the CPU core to execute the break irrespective of the result of the judgment and presence or absence of the break permission signal, when a break enable signal indicating permission of execution of the break is input to the CPU core.

9. A method of controlling a processor, comprising: judging match between an address determined as a breakpoint of a CPU core and an address of a cache at which the CPU core accesses the cache;detecting a cache hit/miss occurred at time of access by the CPU core; andgenerating, based on a result of judgment at the judging and a detected cache hit/miss, a break signal to cause the CPU core to execute a break.

10. The method according to claim 9, further comprising setting a condition to cause the CPU core to execute the break; andoutputting a break permission signal for permitting the break, based on the condition and the detected cache hit/miss, whereinthe generating includes generating the break signal based on the result of judgment and the break permission signal.

11. The method according to claim 10, further comprising: detecting a state of data in the cache, the data stored corresponding to each data address, whereinthe detecting a state includes detecting whether the state is a dirty state or a clean state, the dirty state in which the data has been rewritten by the CPU core at the time of the access, the clean state in which the data has not been rewritten, andthe outputting includes outputting the break permission signal based on the state.

12. The method according to claim 10, wherein the condition includes detection of a cache hit at the detecting a cache hit/miss, andthe outputting includes outputting the break permission signal when the cache hit is detected, without outputting the break permission signal when the cache miss is detected.

13. The method according to claim 10, wherein the condition includes detection of a cache hit at the detecting a cache hit/miss, andthe outputting includes outputting the break permission signal when the cache miss is detected, without outputting the break permission signal when the cache hit is detected.

14. The method according to claim 11, wherein the condition includes detection of the dirty state, andthe outputting includes outputting the break permission signal when the dirty state is detected, without outputting the break permission signal when the clean state is detected.

15. The method according to claim 11, wherein the condition includes detection of the clean state, andthe outputting includes outputting the break permission signal when the clean state is detected, without outputting the break permission signal when the dirty state is detected.

16. The method according to claim 10, further comprising causing the CPU core to execute the break irrespective of the result of the judgment and presence or absence of the break permission signal, when a break enable signal indicating permission of execution of the break is input to the CPU core.