This invention relates generally to data processors, and more specifically to a system and method for implementing a conditional instruction skip.
In the data processing field, a processor executes instructions within sequential memory locations unless one of the instructions directs the processor to jump to a different non-sequential memory location. The processor then continues to sequentially execute instructions at the new non-sequential memory location until another instruction prompts a jump. A jump instruction is typically used when performing an unconditional jump to a non-sequential memory location, while a conditional branch instruction, as its name suggests, is used to jump to the non-sequential memory location upon satisfaction of a predicate condition.
An example operation of a conditional branch instruction is shown in
if (A>B)
A=A+2;
Referring to
Modern microprocessors use a technique called pipelining whereby the processing of an instruction is broken down into subtasks. These subtasks are all performed in parallel for different instructions and this is called a pipeline. Jumps and branches cause a break in the pipeline and so they lose time while some of the stages of processing sit empty. Some processors use a technique called branch prediction in order to ameliorate the performance impact of these pipeline breaks. However, this hardware does not predict perfectly and it can be large.
Although very powerful, conditional branch instructions are also time-consuming and inefficient due to the pipeline stalls. Thus, in high speed applications, the advantages of conditional branch instructions may be negated by the additional processing latency.
The invention may be best understood by reading the disclosure with reference to the drawings, wherein:
In the data processing field, conditional branch functionality is very powerful, yet the execution of the branching instructions is time-consuming and inefficient. The addition of the conditional skip instruction to an assembly language's vocabulary allows processing systems to implement conditional branching functionality without significant reduction in processing speed or efficiency. Embodiments of the present invention will now be described in more detail.
The processor 210 may include a skip-next register 212 to indicate results of skip instructions. When the skip instruction performs a comparison it sets the skip-next register and specifies whether or not the next instruction should be skipped. For instance, when an instruction directing the processor 210 to perform a skip instruction is executed, the processor 210 may set one or more bits within the condition register 212 to indicate the skip instruction results, e.g., “skip” or “don't skip”. The processor 210 may then use the skip-next register to either execute or to skip the next instruction. Although the conditional skip instructions are shown to conditionally skip the next instruction, in some embodiment the execution of the conditional skip instruction may prompt skipping of multiple instructions.
According to a next block 320, the processor 210 determines a condition of the conditional skip instruction is satisfied in response to the results of a predicate function performed at block 310. The processor 210 may determine the results according to the values set in the condition register 212, or directly from the performance of the predicate function.
According to a next block 330, the processor 210 skips a fixed-number of the instructions 222 in response to the satisfaction of the condition.
if (A>B)
A=A+2;
Referring to
Both sets of instructions shown in
Semantic processor 500 includes a direct execution parser (DXP) 550 that controls the processing of packets in the input buffer 530 and a plurality of semantic processing units (SPUs) 560-1 to 560-N within a SPU cluster 560. Each of the SPUs 560-1 to 560-N is configured to process segments of the packets or for perform other operations. The semantic processor 500 includes a memory subsystem 570 for storing or augmenting segments of the packets.
The DXP 550 maintains an internal parser stack 551 of non-terminal (and possibly also terminal) symbols, based on parsing of the current input frame or packet up to the current input symbol. When the symbol (or symbols) at the top of the parser stack 551 is a terminal symbol, DXP 550 compares data DI at the head of the input stream to the terminal symbol and expects a match in order to continue. When the symbol at the top of the parser stack 551 is a non-terminal (NT) symbol, DXP 550 uses the non-terminal symbol NT and current input data DI to expand the grammar production on the stack 551. As parsing continues, DXP 550 instructs one or more of the SPUs 560-1 to 560-N to process segments of the input, or perform other operations.
Semantic processor 500 uses at least three tables. Code segments 222 for SPUs 560-1 to 560-N, including at least one conditional skip instruction, are stored in semantic code table 556. Complex grammatical production rules are stored in a production rule table (PRT) 554. Production rule (PR) codes 553 for retrieving those production rules are stored in a parser table (PT) 552. The PR codes 553 in parser table 552 also allow DXP 550 to detect whether, for a given production rule, a code segment from semantic code table 556 should be loaded and executed by one of the SPUs 560-1 to 560-N. In some embodiments, code segments 222 many be stored within memory subsystem 570, and retrieved by SPUs 560-1 to 560-N according to production rules 555 from the PRT 554.
The production rule (PR) codes 553 in parser table 552 point to production rules in production rule table 554. PR are stored, e.g., in a row-column format or a content-addressable format. In a row-column format, the rows of the table are indexed by a non-terminal symbol NT on the top of the internal parser stack 551, and the columns of the table are indexed by an input data value (or values) DI at the head of the input. In a content-addressable format, a concatenation of the non-terminal symbol NT and the input data value (or values) DI can provide the input to the parser table 552. Preferably, semantic processor 500 implements a content-addressable format, where DXP 550 concatenates the non-terminal symbol NT with 8 bytes of current input data DI to provide the input to the parser table 552. Optionally, parser table 552 concatenates the non-terminal symbol NT and 8 bytes of current input data DI received from DXP 550.
The semantic processor 500 includes a SPU entry point (SEP) dispatcher 580 to allocate one or more of the SPUs 560-1 to 560-N for executing the code segments 222 from semantic code table 556 according to production rules 555 retrieved by the DXP 550. The SEP dispatcher 580 may load allocated SPUs 560-1 to 560-N with code segments 222 from semantic code table 556, or provide the SPUs 560-1 to 560-N one or more addresses to the code segments 222 within the semantic code 556. The SPUs 560-1 to 560-N may then directly load the code segments 222 corresponding the addresses provided by the SEP dispatcher 580.
Once loaded, the code segments 222 may cause one or more SPUs 560-1 to 560-N to perform a conditional instruction skip. Using the example shown in
One skilled in the art will recognize that the concepts taught herein can be tailored to a particular application in many other advantageous ways. In particular, those skilled in the art will recognize that the illustrated embodiments are but one of many alternative implementations that will become apparent upon reading this disclosure.
The preceding embodiments are exemplary. Although the specification may refer to an “one”, “another”, or “some” embodiment(s) in several locations, this does not necessarily mean that each such reference is to the same embodiment(s), or that the feature only applies to a single embodiment.