Patent Application
20070300086
The several embodiments described herein are solely for the purpose of illustration. Embodiments may include any currently or hereafter-known versions of the elements described herein. Therefore, persons in the art will recognize from this description that other embodiments may be practiced with various modifications and alterations.
Referring to
For purposes of the present description, each of the processor cores 102 and 104 comprise systems for executing program code. The program code may comprise one or more threads of one or more software applications. Each of the processor cores 102 and 104 may include or otherwise be associated with dedicated registers, stacks, queues, etc. that are used to execute program code and/or one or more of these elements may be shared there between.
As illustrated in
In some embodiments, the first circuit 103 may comprise, but is not limited to, a ring oscillator and the second circuit 105 may comprise, but is not limited to, a ring oscillator. In some embodiments, the first processor core 102 may comprise two or more ring oscillators and the second processor core 104 may comprise two or more ring oscillators. The generated data may comprise a frequency difference or an oscillation frequency associated with a respective ring oscillator according to some embodiments. The nature and usage of such data will be described in detail below.
The processor core scheduler 106 may be implemented in hardware, firmware, or software. In some embodiments, the processor core scheduler 106 may request the data from the first circuit 103 and the second circuit 105 and may receive the data in return. The processor core scheduler 106 may assign a thread to the first processor core 102 or to the second processor core 104 based on the first data and the second data. The foregoing structure may provide even processor core wear and therefore decrease the probability of a system failure over time.
Now referring to
At 201, a first data associated with a first processor core may be received. The first data may indicate wear of the first processor core. According to some embodiments, the first data comprises an oscillation frequency of a ring oscillator disposed in the first processor core.
At 202, a second data associated with a second processor core may be received. The second data may also indicate wear associated with the second processor core. The second data may be received from a second circuit in some embodiments and the second data may comprise an oscillation frequency of the second circuit. As described above, the first processor core and the second processor core may be disposed on a single processor die. In some embodiments, the first processor core and the second processor core are disposed on different processor dies.
Next, at 203, a first thread is assigned to the first processor core or to the second processor core based on the first data and the second data. According to some embodiments of 203, the processor core scheduler 106 assigns the first thread based on wear (or aging) of the first processor core 102 and the second processor core 104. In this regard, the first data and the second data may indicate that the second processor core 104 exhibits greater wear than the first processor core 102. Accordingly, in order to distribute processor core wear evenly throughout the processor die 101, the processor core scheduler 106 may assign the first thread to the first processor core 102 at 203.
At
Each processor core 302, 304, 308, 310 may comprise a circuit 303, 305, 309, 311, respectively, to generate data. The data may indicate wear of the associated processor cores. Each of circuits 303, 305, 309, 311 may comprise a ring oscillator circuit, with the generated data comprising of an oscillation frequency of the ring oscillator circuit. In some embodiments, the first circuit 303, the second circuit 309, the third circuit 305, and the fourth circuit 311 may each comprise two or more ring oscillator circuits.
The processor core scheduler 306 may be implemented in software, firmware, or hardware. In some embodiments, the processor core scheduler 306 may request the above-mentioned data from each of circuits 303, 305, 309, 311 and may receive the data in return. The processor core scheduler 306 may assign a thread to processor cores 302, 304, 308, 310 based on each core's respective data. In some embodiments, the processor core scheduler 306 may assign a first thread to a processor core 302, 308 associated with the first processor die 301 and may assign a second thread to a processor core 304, 310 associated with the second processor die 312 based on the data.
System 400 of
Each processor core 402, 404, 408, 410 may comprise one or more circuits 403, 405, 409, 411 respectively to generate data. The data may be generated periodically or in response to a request from the processor core scheduler 406, and may be stored in the database 412. As illustrated in
The agent 407 may receive data from each circuit 403, 409, 405, 411 for the above mentioned data. In some embodiments, the agent may assess the degradation and/or classify the wear of each processor core 402, 408, 404, 410 based on the received data. The agent 407 may be implemented in hardware, firmware, or software. Information generated by the agent 407 may be stored in database 412 in association with a respective processor core. In some embodiments, the agent may continuously poll each circuit 403, 409, 405, 411 at predetermined intervals.
The processor core scheduler 406 may be implemented in firmware, hardware, or software. In some embodiments, the processor core scheduler 406 may request the data from each of circuits 403, 405, 409, 411 via the agent 407 and may receive the data in return. The processor core scheduler 406 may assign a thread to processor cores 402, 404, 408, 410 based on each core's respective data. In some embodiments, the processor core scheduler 406 will assign a thread to a processor core 402, 404, 408, 410 only if the data shows that a wear or degradation of the processor core is less than a predetermined percentage.
In some embodiments, the processor core scheduler 406 uses data from both of the circuits 403 to assign a thread to one of the processor cores 403, 404, 408, 410. The processor core scheduler 406 may determine an average of such data in order to facilitate comparison of the processor core 402 with the processor cores 404, 408, 410. In some embodiments, the average may comprise a weighted average based on the location of each circuit 403, 405, 409, 411. For example, a hotter region of a processor core 402, 404, 408, 410 may degrade faster than a cooler region of the processor core 402, 404, 408, 410. Accordingly, data generated by circuits 403, 405, 409, 411 located within known regions of the processor core 402, 404, 408, 410 may be weighted based on the expected relative temperature of their respective regions.
The memory module 414 may store, for example, applications, programs procedures, and/or modules that store instructions to be executed. The memory module 414 may comprise, according to some embodiments, any type of memory for storing data, such as a Single Data Rate Random Access Memory (SDR-RAM), a Double Data Rate Random Access Memory (DDR-RAM), or a Programmable Read Only Memory (PROM).
The database 412 may store data used by the processor core scheduler 406 to assign threads to processor cores 402, 404, 408, 410. In some embodiments, the agent 407 stores the data in the database 412. The database 412, may be comprised of, but not limited to, non-volatile memory, flash memory, magnetic media, optical media, read only memory, or any other available media.
At
Next, at 702, a second oscillation frequency associated with a second processor core may be received. According to some embodiments of 702, the agent 407 receives a second oscillation frequency from another one of circuits 403, 405, 409, 411 at 702, and stores the frequency in the database 412. At 703, a first frequency difference is determined between a first initial frequency and the first oscillation frequency. The first initial frequency may be associated with a same processor core as the first oscillation frequency. In this regard, the first initial frequency may indicate a previous (e.g., at fabrication time) oscillation frequency of a circuit associated with the first processor core. The first initial frequency may be determined from the
At 704, a second frequency difference is determined between a second initial frequency and the second oscillation frequency. Again, the second initial frequency may be determined from the
At 705, the first frequency difference is compared to the second frequency difference. The first frequency difference may provide an indication of a degree of wear experienced by the first processor core since determination of the first initial frequency. Similarly, the second frequency difference may provide an indication of a degree of wear experienced by the second processor core since determination of the second initial frequency. In some embodiments, a greater frequency difference indicates a greater amount of wear.
Accordingly, at 706, the processor core scheduler associates a thread with the first processor core if the first frequency difference is less than the second frequency difference. If the first frequency difference is greater than the second frequency difference, then the processor core scheduler may associate the thread with the second processor core at 707. In some embodiments, process 700 may be periodically repeated to assess relative degradation after a large interval, relative to a processor clock cycle, to avoid significant consumption of processor core resources. In between the repeated intervals, threads may be sent to a less degraded core until a next assessment of relative degradation. Some embodiments of process 700 may provide leveling of wear across two or more processor cores. In some embodiments, a usage uniformity of between five and ten percent of each processor core 402, 404, 408, 410 may be obtained.
Various modifications and changes may be made to the foregoing embodiments without departing from the broader spirit and scope set forth in the appended claims.
