Makoto Amamiya et al., “Datarol: A Massively Parallel Architecture for Functional Langauge,” Parallel and Distributed Processing, IEEE 1990, TH0328-5/90/0000/0726. |
P. K. Dubey et al., “Single-Program Speculative Multithreading (SPSM) Architecture: Compiler Assisted Fine Grained Multi-threading,” Proc. Int'l Conf. On Parallel Arch. and Comp. Tech., PACT '95, Jun. 27-29, 1995, pp. 109-121, Limassol, Cyprus. |
J. Gonzalez et al. “Speculative Execution Via Address Prediction and Data Prefetching,” Proc. of the 1997 Int'l Conf. on Supercomputing, Vienna, ICS '97, Jul. 7-11, 1997, pp. 196-203. |
A. Sodani et al. “Dynamic Instruction Reuse,” 24th Annual Int'l Symposium on Computer Architecture, ISCA '97, Denver, Jun. 2-4, 1997, ACM, vol. 24, Jun. 2, 1997, p. 194-205. |
G. S. Sohi, “Instruction Issue Logic For High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers,” IEEE Transactions on Computers, vol. 39, No. 3, Mar. 1, 1990, pp. 349-359. |
Jenn-Yuan Tsai et al., “The Superthreaded Architecture: Thread Pipelining with Run-time Data Dependence Checking and Control Speculation” Parallel Architectures and Compilation Techniques, 1996, Proc. of the PACT '96, IEEE Computer Soc., Oct. 20-23, 1996, pp. 35-46. |
G. Tyson et al., “Improving the Accuracy and Performance of Memory Communication Through Renaming,” Proc. of the 30th Annual IEEE/ACM Int'l Symp. On Microarchitecture, Micro-30, Research Triangle, NC, Dec. 1-3, 1997, Proc. of the Int'l Symp. On Microarch Los Alamitos CA, Dec. 1, 1997, pp. 218-227. |
M. Franklin, “The Multiscalar Architecture,” Ph.D. Dissertation, Univ. of Wisconsin, 1993, pp. i, ii, v-ix, 50-73, 75-81, 86-107, 109-134, and 153-161. |
J. Smith et al., “The Microarchitecture of Superscaler Processors,” Proceedings of IEEE, vol. 83, No. 12, Dec. 1995, pp. 1609-1624. |
D. Tullsen et al., “Simultaneous Multithreading: Maximizing On-Chip Parallelism,” The 22nd International Symposium on Computer Architecture, Jun. 1995, pp. 392-403. |
G. Sohi et al., “Multiscaler Processors.” The 22nd Annual International Symposium on Computer Architecture, Jun. 1995, pp. 414-425. |
E. Rotenberg et al., “Trace Processors,” The 30th International Symposium on Microarchitecture, Dec. 1997, pp. 138-148. |
M. Franklin et al., “ARB: A Hardware Mechanism for Dynamic Reordering of Memory References. IEEE Transactions on Computers”, vol. 45, No. 5, May 1996, pp. 552-571. |
J. Tsai et al., “The Superthreaded Architecture: Thread Pipelining with Run-Time Data Dependence Checking and Control Speculation,” Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques, Oct. 1996, pp. 35-46. |
P. Song, “Multithreading Comes of Age,” Microprocessor Report, Jul. 14, 1997, pp. 13-18. |
Q. Jacobson et al., “Path-Based Next Trace Prediction,” Proceedings of the 30th International Symposium on Microarchitecture, Dec. 1997, pp. 14-23. |
Q. Jacobson et al., “Control Flow Speculation in Multiscalar Processors,” Proceedings of the 3rd International Symposium on High-Performance Computer Architecture, Feb. 1997, pp. 218-229. |
R. Nair, “Dynamic path-based branch correlation,” Proceedings of the 28th International Symposium on Microarchitecture, Dec. 1995, pp. 15-23. |
S. Palacharla et al., “Complexity-Effective Superscalar Processors,” The 24th Annual International Symposium on Computer Architecture, pp. 206-218, Jun. 1997. |
M. Lipasti et al., “Value Locality and Load Value Prediction,” Proceedings of the Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 1996, ASPLOS-VII, pp. 138-147. |
Written Opinion cited in PCT Application No. PCT/US98/126501 corresponding to U.S. application Ser. No. 08/992,375. |
EPO Search Report dated Jun. 10, 2002 for European App. 98 96 3903 corresponding to U.S. application 08/992,735. |