Claims
- 1. A boot address translation apparatus, wherein a microprocessor has an address space and requests instructions from the address space by issuing a request over a bus including an address, which is in the address space, of a desired instruction, wherein, following a microprocessor reset, the microprocessor requests a first boot instruction which is pointed to by a fixed address, and wherein the fixed address comprises a plurality of address bits, the apparatus comprising:
- a boot detector, which outputs a booting signal following a microprocessor reset;
- an address blocking means, responsive to said booting signal and coupled to the bus, for blocking a portion of said address bits of the fixed address;
- an address substitution means, responsive to said booting signal and coupled to the bus, for substituting a substituted plurality of address bits for said blocked address bits, when the fixed address does not point to a physical address and said booting signal is asserted, said substituted plurality of address bits, when combined with unblocked address bits of the fixed address, forming a physical address in an instruction memory; and
- means for disabling said address substitution means after the microprocessor is configured to only make requests from valid addresses.
- 2. The apparatus of claim 1, wherein said address blocking means and said address substitution means comprise a multi-bit input, 2-to-1 multiplexer with a selection control input responsive to said booting signal.
- 3. The apparatus of claim 1, wherein addresses on the bus include parity bits meeting a parity criterium, and wherein said address substitution means further comprises means for including substituted parity bits, wherein said substituted parity bits meet said parity criterium.
Parent Case Info
This is a Division of application Ser. No. 08/088,562 filed Jul. 6, 1993 now U.S. Pat. No. 5,435,001.
US Referenced Citations (10)
Foreign Referenced Citations (6)
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Divisions (1)
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Number |
Date |
Country |
Parent |
88562 |
Jul 1993 |
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