Patent Application
20170364473
This application relates generally to circuit synchronization and more particularly to program counter alignment across a reconfigurable hum fabric.
Electronic circuits are used in a wide variety of applications and products for many purposes, including communication, audio/video, security, general and special purpose computing, data compression, signal processing, and medical devices, to name a few. Current consumer trends focus on increasingly powerful devices with increased portability. It can prove challenging to achieve more processing power while simultaneously improving energy efficiency. Improved energy efficiency translates to longer battery life, which is an important factor in the design of portable electronic devices. To enable complex functionality along with efficiency in power consumption, designers often utilize a system-on-chip (SoC). SoCs are constructed using a variety of modules and/or sub-systems used to perform specific functions. These are integrated together with a communication medium (such as a system bus). Each module could have different timing requirements. The integration of modules with varying clock and timing requirements can create challenges in design, testing, and verification of complex SoCs.
Circuit synchronization and timing are important considerations in the design of a complex circuit or SoC. In practice, the arrival time of a signal can vary for many reasons. The various values on input data can cause different operations or calculations to be performed, introducing a delay in the arrival of a signal. Furthermore, operating conditions such as temperature can affect the speed at which circuits may perform. Variability in the manufacture of parts can also contribute to timing differences. Properties such as the threshold voltage of transistors, the width of metallization layers, and dopant concentrations are examples of parameters that can vary during the production of integrated circuits, potentially affecting timing. A large-scale architecture with many subsystems can typically result in a large number and variety of interacting clock domains. Synchronizing all of the clock domains can be rendered difficult by engineering costs, power consumption, and project-level risks. Accordingly, such architectures and designs increasingly utilize multiple asynchronous clock domains. The use of a variety of different domains can make timing analysis and synchronization even more challenging.
The electronic systems with which people interact on a daily basis contain electronic integrated circuits or “chips”. The chips result from stringent specifications and are designed to perform a wide variety of functions in the electronic systems. The chips support and enable the electronic systems to perform their functions effectively and efficiently. The chips are based on highly complex circuit designs, system architectures and implementations, and are fabrication processes. The chips are integral to the electronic systems. The chips implement functions such as communications, processing, and networking, whether the electronic systems are applied to business, entertainment, or consumer electronics purposes. The electronic systems routinely contain more than one chip. The chips implement critical functions including power management, audio codecs, computation, storage, and control. The chips compute algorithms and heuristics, handle and process data, communicate internally and externally to the electronic system, and so on. Since there are so many computations that must be performed, any improvements in the efficiency of the computations have a significant and substantial impact on overall system performance. As the amount of data to be handled increases, the approaches that are used must be not only effective, efficient, and economical, but must also be scalable.
Disclosed embodiments provide for program counter alignment across a reconfigurable hum fabric. Information on logical distances between circuits on a semiconductor chip can be obtained. A plurality of clusters within the circuits on the semiconductor chip can be determined, where a cluster within the plurality of clusters can be synchronized to a tic cycle boundary. A plurality of counter initializations can be calculated, where the counter initializations can compensate for the tic cycle count separation across the plurality of clusters. A plurality of counters can be initialized, with a counter from the plurality of counters being associated with each cluster from the plurality of clusters, where the counters from the plurality of counters can be distributed across the plurality of clusters, and where the initializing can be based on the counter initializations that were calculated. The plurality of counters can be started to coordinate calculation across the plurality of clusters.
Reconfigurable arrays or clusters that include processing elements, switching elements, clusters of clusters, etc., have many applications where high speed data transfer and processing are advantageous. Global distribution of signals such as clocks, data, controls, status flags, etc. are often required for proper system operation. However, the reconfigurable arrays including a reconfigurable fabric, may not support such distribution because of physical limitations of design styles, system architectures, fabrication capabilities, etc. Instead, the global signals can be propagated across the reconfigurable arrays or fabric. Propagation can be based on determining how to initialize the reconfigurable fabric in order to most efficiently propagate the global signals. The propagation can be based on hum generation signals.
Disclosed is a processor-implemented method for circuit synchronization comprising: obtaining information on logical distances between circuits on a semiconductor chip; determining a plurality of clusters within the circuits on the semiconductor chip, wherein a cluster within the plurality of clusters is synchronized to a tic cycle boundary; evaluating a tic cycle count separation across the plurality of clusters using the information on the logical distances; calculating a plurality of counter initializations wherein the counter initializations compensate for the tic cycle count separation across the plurality of clusters; initializing a plurality of counters, with a counter from the plurality of counters being associated with each cluster from the plurality of clusters, wherein the counters from the plurality of counters are distributed across the plurality of clusters, and wherein the initializing is based on the counter initializations that were calculated; and starting the plurality of counters to coordinate calculation across the plurality of clusters. In embodiments, the starting the plurality of counters includes starting a first counter in a first cluster, from the plurality of clusters, followed by starting a second counter in a second cluster, from the plurality of clusters. In embodiments, a computer program product embodied in a non-transitory computer readable medium for circuit synchronization comprising code which causes one or more processors to perform operations of: obtaining information on logical distances between circuits on a semiconductor chip; determining a plurality of clusters within the circuits on the semiconductor chip, wherein a cluster within the plurality of clusters is synchronized to a tic cycle boundary; evaluating a tic cycle count separation across the plurality of clusters using the information on the logical distances; calculating a plurality of counter initializations wherein the counter initializations compensate for the tic cycle count separation across the plurality of clusters; initializing a plurality of counters, with a counter from the plurality of counters being associated with each cluster from the plurality of clusters, wherein the counters from the plurality of counters are distributed across the plurality of clusters, and wherein the initializing is based on the counter initializations that were calculated; and starting the plurality of counters to coordinate calculation across the plurality of clusters.
Various features, aspects, and advantages of various embodiments will become more apparent from the following further description.
The following detailed description of certain embodiments may be understood by reference to the following figures wherein:
Techniques are disclosed for circuit synchronization, and more particularly, for program counter alignment across a reconfigurable hum fabric. Reconfigurable fabrics that run at a very fast hum frequency can provide an extremely powerful dataflow processing system for handling massive amounts of data and calculations, such as that required for machine learning, deep analytics, and other big data applications. The electronics and semiconductor industries are compelled by commercial, military, and other market segments to improve the semiconductor chips and systems that they design, develop, implement, fabricate, and deploy. Improvements of the semiconductor chips are measured based on many factors including design criteria such as the price, dimensions, speed, power consumption, heat dissipation, feature sets, compatibility, etc. These chip measurements find their ways into designs of the semiconductor chips and the capabilities of the electronic systems that are built from the chips. The semiconductor chips and systems are deployed in many market segments including commercial, medical, consumer, educational, financial, etc. The applications include computation, digital communications, control and automation, etc., naming only a few. The abilities of the chips to perform basic logical operations and to process data, at high speed, are fundamental to any of the chip and system applications. The abilities of the chips to transfer very large data sets have become particularly critical because of the demands of many applications. Disclosed embodiments provide fundamental improvements to the architectures and chips used for processing big data applications, such as machine learning.
Chip, system, and computer architectures have traditionally relied on controlling the flow of data through the chip, system, or computer. In these architectures, such as the classic Van Neumann architecture where memory is shared for storing instructions and data, a set of instructions is executed to process data. With such an architecture, referred to as a “control flow”, the execution of the instructions can be predicted and can be deterministic. That is, the way in which data is processed is dependent upon the point in a set of instructions at which a chip, system, or computer is operating. In contrast, a “dataflow” architecture is one in which the data controls the order of operation of the chip, system, or computer. The dataflow control can be determined by the presence or absence of data. Dataflow architectures find applications in many areas including the fields of networking and digital signal processing, as well as other areas in which large data sets must be handled such as telemetry and graphics processing.
Dataflow processors can be applied to many applications where large amounts of data such as unstructured data are processed. Typical processing applications for unstructured data can include speech and image recognition, natural language processing, bioinformatics, customer relationship management, digital signal processing (DSP), graphics processing (GP), network routing, telemetry such as weather data, data warehousing, and so on. Dataflow processors can be programmed using software and can be applied to highly advanced problems in computer science such as deep learning. Deep learning techniques can include an artificial neural network, a convolutional neural network, etc. The success of these techniques is highly dependent on large quantities of data for training and learning. The data-driven nature of these techniques is well suited to implementations based on dataflow processors. The dataflow processor can receive a dataflow graph such as an acyclic dataflow graph, where the dataflow graph can represent a deep learning network. The dataflow graph can be assembled at runtime, where assembly can include calculation input/output, memory input/output, and so on. The assembled dataflow graph can be executed on the dataflow processor.
The dataflow processors can be organized in a variety of configurations. One configuration can include processing element quads with arithmetic units. A dataflow processor can include one or more processing elements (PE). The processing elements can include a processor, a data memory, an instruction memory, communications capabilities, and so on. Multiple PEs can be grouped, where the groups can include pairs, quads, octets, etc. The PEs arranged in arrangements such as quads can be coupled to arithmetic units, where the arithmetic units can be coupled to or included in data processing units (DPU). The DPUs can be shared between and among quads. The DPUs can provide arithmetic techniques to the PEs, communications between quads, and so on.
The dataflow processors, including dataflow processors arranged in quads, can be loaded with kernels. The kernels can be a portion of a dataflow graph. In order for the dataflow processors to operate correctly, the quads can require reset and configuration modes. Processing elements can be configured into clusters of PEs. Kernels can be loaded onto PEs in the cluster, where the loading of kernels can be based on availability of free PEs, an amount of time to load the kernel, an amount of time to execute the kernel, and so on. Reset can begin with initializing up-counters coupled to PEs in a cluster of PEs. Each up-counter is initialized with a value −1 plus the Manhattan distance from a given PE in a cluster to the end of the cluster. A Manhattan distance can include a number of steps to the east, west, north, and south. A control signal can be propagated from the start cluster to the end cluster. The control signal advances 1 cluster per cycle. When the counters for the PEs all reach 0 then the processors have been reset. The processors can be suspended for configuration, where configuration can include loading of one or more kernels onto the cluster. The processors can be enabled to execute the one or more kernels. Configuring mode for a cluster can include propagating a signal. Clusters can be preprogrammed to enter configuration mode. A configuration mode can be entered. Various techniques, including direct memory access (DMA) can be used to load instructions from the kernel into instruction memories of the PEs. The clusters that were pre-programmed into configuration mode can be preprogrammed to exit configuration mode. When configuration mode has been exited, execution of the one or more kernels loaded onto the clusters can commence. In embodiments, clusters can be reprogrammed and during the reprogramming switch instructions used for routing are not interfered with so that routing continues through a cluster.
Dataflow processes that can be executed by dataflow processor can be managed by a software stack. A software stack can include a set of subsystems, including software subsystems, which may be needed to create a software platform. A complete software platform can include a set of software subsystems required to support one or more applications. A software stack can include offline operations and online operations. Offline operations can include software subsystems such as compilers, linker simulators, emulators, and so on. The offline software subsystems can be included in a software development kit (SDK). The online operations can include dataflow partitioning, dataflow graph throughput optimization, and so on. The online operations can be executed on a session host and can control a session manager. Online operations can include resource management, monitors, drivers, etc. The online operations can be executed on an execution engine. The online operations can include a variety of tools which can be stored in an agent library. The tools can include BLAS™, CONV2D™, SoftMax™, and so on.
Software to be executed on a dataflow processor can include precompiled software or agent generation. The pre-compiled agents can be stored in an agent library. An agent library can include one or more computational models which can simulate actions and interactions of autonomous agents. Autonomous agents can include entities such as groups, organizations, and so on. The actions and interactions of the autonomous agents can be simulated to determine how the agents can influence operation of a whole system. Agent source code can be provided from a variety of sources. The agent source code can be provided by a first entity, provided by a second entity, and so on. The source code can be updated by a user, downloaded from the Internet, etc. The agent source code can be processed by a software development kit, where the software development kit can include compilers, linkers, assemblers, simulators, debuggers, and so one. The agent source code that can be operated on by the software development kit can be in an agent library. The agent source code can be created using a variety of tools, where the tools can include MATMUL™, Batchnorm™, Relu™, and so on. The agent source code that has been operated on can include functions, algorithms, heuristics, etc., that can be used to implement a deep learning system.
A software development kit can be used to generate code for the dataflow processor or processors. The software development kit can include a variety of tools which can be used to support a deep learning technique or other technique which requires processing of large amounts of data such as unstructured data. The SDK can support multiple machine learning techniques such as machine learning techniques based on GEMM™, sigmoid, and so on. The SDK can include a low-level virtual machine (LLVM) which can serve as a front end to the SDK. The SDK can include a simulator. The SDK can include a Boolean satisfiability solver (SAT solver). The SDK can include an architectural simulator, where the architectural simulator can simulate a dataflow processor or processors. The SDK can include an assembler, where the assembler can be used to generate object modules. The object modules can represent agents. The agents can be stored in a library of agents. Other tools can be included in the SDK. The various techniques of the SDK can operate on various representations of a flow graph.
Direct memory access can be applied to improve communication between processing elements, switching elements etc. of a fabric or cluster of such elements. Since communication such as the transfer of data from one location to another location can be a limiting factor in system performance, increased communication rate and efficiency can directly impact speed. Data is obtained from a first switching element within a plurality of switching elements. The first switching element is controlled by a first circular buffer. The data is sent to a second switching element within the plurality of switching elements. The second switching element is controlled by a second circular buffer. The obtaining data from the first switching element and the sending data to the second switching element included a direct memory access. The first switching element and the second switching element can be controlled by a third switching element within the plurality of switching elements.
A circuit according to disclosed embodiments is configured to provide hum generation such that the circuit can operate at a hum frequency. A hum frequency can be a frequency at which multiple clusters within the circuit self-synchronize to each other. The hum generation circuit can be referred to as a fabric. The hum generation fabric can form a clock generation structure. Each module contains one or more functional circuits such as adders, shifters, comparators, and/or flip flops, among others. These functional circuits each perform a function over a finite period of time. The operating frequency of a module is bounded by the slowest functional circuit within the module. In embodiments, each functional circuit operates over one cycle or tic of the clock. The tic cycle can be a single cycle of the hum generated self-clocking signal. With a self-clocking design, it can be a challenge to select a hum frequency that is compatible with each of the various functional logic circuits within each cluster. If the hum frequency is not correct, then the overall operation of the integrated circuit might be compromised.
The flow 100 includes determining a plurality of clusters 120 within the circuits on the semiconductor chip. Semiconductor chips can include many circuits, where the circuits can be simple or complex, digital or analog, etc. One or more of the circuits can include a reconfigurable fabric on the semiconductor chip. The reconfigurable fabric can include processing elements, switching elements, interface elements, etc. In embodiments, an element can be configured to be a processing element, a switching element, an interface element, a storage element, and so on. A cluster can include a region within the semiconductor chip. The semiconductor chip can include one or more clusters, and the clusters can be grouped together. The clusters can communicate with their nearest neighbors, where the nearest neighbors can be a Manhattan step away. The communications can include control, data, configuration data, etc. A cluster within the plurality of clusters can be synchronized to a tic cycle boundary 122. Multiple clusters can be synchronized to the same tic cycle boundary, to different tic cycle boundaries, and so on. The reconfigurable fabric can be synchronized by hum generation signals.
The flow 100 includes evaluating a tic cycle count separation 130 across the plurality of clusters using the information on the logical distances. The logical distance can be based on Manhattan distances as described above. The tic cycle count separation can be based on the number of processing elements (PE), number of clusters, etc., in a group. In embodiments, the tic cycle count separation between two neighboring clusters, from the plurality of clusters, can be a single tic count. The single tic count can correspond to a Manhattan step (north, south, east, or west). In other embodiments, the tic cycle count separation between two neighboring clusters, from the plurality of clusters, can be a two tic count. A neighboring cluster located on a diagonal can be two Manhattan steps away. For example, for a 3×3 group, the tic cycle count separation between the block in the southwestern-most corner and the northeastern-most corner can be 5 since the count to the southwestern-most corner is one from cluster zero. Further, at least one tic cycle can occur in order for one or more operations to be performed. The tic cycle count separation can be determined based on Manhattan distances. Other distance geometries can be included that can be based on diagonal distances. The logical distances comprise sequential tic cycle counts. In embodiments, a tic cycle, from the tic cycle count separation, can define alignment edges for synchronized operation of logic. The flow 100 includes a propagation timing 132 of a deterministic value from a first cluster to a second cluster, where the first cluster and the second cluster are from the plurality of clusters, and wherein the first cluster is adjacent to the second cluster. The propagation timing can be based on the deterministic value that can include a propagation timing equal to 1 tic cycle. Other propagation timing values can be included.
The flow 100 includes calculating a plurality of counter initializations 140 where the counter initializations compensate for the tic cycle count separation across the plurality of clusters. Returning to the 3×3 group example, and by referencing discussions presented elsewhere, the counter initializations of elements of a group depend on the location of a particular element within the group. The element can be a processing element, a switching element, a cluster, and so on. Count separations for processing elements within a cluster, clusters within clusters etc., can be determined based on Manhattan or other separations. The one or more counters can be initialized based on the location of the processing element or cluster position within a cluster. As discussed in the 3×3 example above and elsewhere, the counter initializations can vary from 5 in the southwestern-most cluster or PE, to 1 in the northeastern-most cluster or PE. Note that the counter initializations can be equal along northwest-to-southeast diagonals in the clusters. The flow 100 includes initializing a plurality of counters 150, with a counter from the plurality of counters being associated with each cluster from the plurality of clusters, where the counters from the plurality of counters are distributed across the plurality of clusters, and where the initializing is based on the counter initializations that were calculated. The counters can be initialized on the Manhattan distance. The counters can be initialized based on tic cycle count separation. One counter, from the plurality of counters, can be in each of the plurality of clusters. Multiple counters can be in each of the plurality of clusters. Various types of counters can be used. In embodiments, the plurality of counters comprises down counters. The plurality of counters can be set to specific values, based on the logical distances, at time of boot for the semiconductor chip. The setting of the counters at time of boot can be used to reset the fabric, initialize the fabric, and so on. In embodiments, the specific values can provide for synchronized startup of operation across a reconfigurable fabric. The initializing can include memory accesses to values such as initialization values for the counters. In embodiments, the initializing of the plurality of counters can occur during hardware paging.
The flow 100 includes starting the plurality of counters 160 to coordinate calculation across the plurality of clusters. The counters can be used to control propagation of signals including propagated global signals, status signals, data, and so on. The counters can be started as a result of a reset of processing elements, reset of switching elements, reset of clusters, etc. The starting the plurality of counters can include starting a first counter 162 in a first cluster, from the plurality of clusters, followed by starting a second counter 164 in a second cluster, from the plurality of clusters. The starting counters can include starting a third counter in a third cluster, and so on. In embodiments, the second cluster can be a neighboring cluster, from the plurality of clusters, to the first cluster. Other counters can be started to coordinate calculation across the plurality of clusters, whether the clusters are adjacent or not. Various embodiments of the flow 100 may be included in a computer program product embodied in a non-transitory computer readable medium that includes code executable by one or more processors.
In embodiments, one or more switching elements, processing elements, clusters, etc., of one or more clusters of switching elements, etc., can be placed into a sleep state. A switching element can enter a sleep state based on processing an instruction that places the switching element into the sleep state. The switching element can be woken from the sleep state as a result of valid data being presented to the switching element of a cluster. Recall that a given switching element can be controlled by a circular buffer. The circular buffer can contain an instruction to place one or more of the switching elements into a sleep state. The circular buffer can remain awake while the switching element controlled by the circular buffer is in a sleep state. In embodiments, the circular buffer associated with the switching element can be placed into the sleep state along with the switching element. The circular buffer can wake along with its associated switching element. The circular buffer can wake at the same address as when the circular buffer was placed into the sleep state, at an address that can continue to increment while the circular buffer was in the sleep state, etc. The circular buffer associated with the switching element can continue to cycle while the switching element is in the sleep state, but instructions from the circular buffer may not be executed. The sleep state can include a rapid transition to sleep state capability, where the sleep state capability can be accomplished by limiting clocking to portions of the switching elements. In embodiments, the sleep state can include a slow transition to sleep state capability, where the slow transition to sleep state capability can be accomplished by powering down portions of the switching elements. The sleep state can include a low power state.
The obtaining data from a first switching element and the sending the data to a second switching element can include a direct memory access (DMA). A DMA transfer can continue while valid data is available for the transfer. A DMA transfer can terminate when it has completed without error, or when an error occurs during operation. Typically, a cluster that initiates a DMA transfer will request to be brought out of sleep state when the transfer is completed. This waking is achieved by setting control signals that can control the one or more switching elements. Once the DMA transfer is initiated with a start instruction, a processing element or switching element in the cluster can execute a sleep instruction to place itself to sleep. When the DMA transfer terminates, the processing elements and/or switching elements in the cluster can be brought out of sleep after the final instruction is executed. Note that if a control bit can be set in the register of the cluster that is operating as a slave in the transfer, that cluster can also be brought out of sleep state (if it is asleep during the transfer).
The cluster that is involved in a DMA and can be brought out of sleep after the DMA terminates can determine that it has been brought out of a sleep state based on the code that is executed. A cluster can be brought out of a sleep state based on the arrival of a reset signal and the execution of a reset instruction. The cluster can be brought out of sleep by the arrival of valid data (or control) following the execution of a switch instruction. A processing element or switching element can determine why it was brought out of a sleep state by the context of the code that the element starts to execute. A cluster can be awoken during a DMA operation by the arrival of valid data. The DMA instruction can be executed while the cluster remains asleep as the cluster awaits the arrival of valid data. Upon arrival of the valid data, the cluster is woken and the data stored. Accesses to one or more data random access memories (RAM) can be performed when the processing elements and the switching elements are operating. The accesses to the data RAMs can also be performed while the processing elements and/or switching elements are in a low power sleep state. Various embodiments of the flow 200 may be included in a computer program product embodied in a non-transitory computer readable medium that includes code executable by one or more processors.
A global signal to be propagated across a cluster, multiple clusters, the semiconductor chip, and so on, originates as an event. To propagate the global signals, a propagator can be used to rebroadcast any timed global signal. Each propagator can perform various operations including: contain a programmed value indicating its Manhattan distance from cluster zero; receive a signal assertion as input from one or more cardinal directions (north, south, east, or west); contain a countdown register, loaded with a reset value upon assertion of a signal input, where the reset value can be a function of its Manhattan distance value and a maximum value distance; ignore the assertion of any other propagated global signal when a countdown is currently in progress; and act upon the signal's meaning only when the countdown register reaches zero.
A timed global signal can be asserted in the southwestern-most propagator 300. The southwestern-most corner can have a Manhattan distance of 1 from the origin cluster, cluster zero. Since the northeastern-most corner is an additional 4 steps using Manhattan distance, then the count in the southwestern-most corner is calculated to be 5. The count can be used by a program counter which can be used to control propagation. The counts and distances for the remaining cells similarly can be calculated. The distance values increase while the count values decrease. Note that the count values are equal and distance values are equal along northwest-to-southeast diagonals because the cells along the diagonals are equidistant from the southwestern-most cell in a Manhattan distance sense.
Some signals that can be utilized by the semiconductor chip can be required across the entire chip. These global signals can include data, control, clock, status, etc. The design of the chip can directly impact distribution of these global signals due to limitations on physical design such as the numbers of layers of interconnect. The global signals can be distributed across the semiconductor chip via a propagation technique. Synchronization of signal propagation is critical to effective chip operation. The reconfigurable fabric can be synchronized by hum generation signals.
An 8×8 group of clusters included in an example semiconductor chip is shown with count distances. Signals including global signals can be coupled to the 8×8 group using peripheral logic. The peripheral logic can include peripheral logic that couples vertically to the 8×8 group 410, and can include peripheral logic that couples horizontally to the 8×8 group 412. Since global signals such as clock, data, control, status etc. may not be physically available globally, these global signals can be propagated across the 8×8 group of clusters. In order to perform the signal propagation, the count distances to various clusters can be calculated. The count distances can be based on Manhattan distances, where one count step can be made to the north, south, east, or west. The count distance to the southwestern-most cell is calculated to be 1 since it is one step from the origin cluster zero. To get to the other clusters within the 8×8 group of clusters, steps can be counted from the southwestern-most corner of the 8×8 group. So, a step to the north, south, east or west counts as one step, while a step along a diagonal from southwest-to northeast counts as two steps, one step to the east or west, and one step to the north or south. By proceeding through the 8×8 group of clusters, the Manhattan distances to each cluster from the southwestern-most cluster can be calculated. Note that clusters along northwest-to-southeast diagonals have equal count distances.
Communication between and among clusters is shown. A test controller 510 can receive control and configuration signals, and can communicate control and data/configuration signals to clusters. Since communications can be based on Manhattan directions and distances, a given cluster may communicate with neighboring clusters that are located to the north, south, east or west of the given cluster. Communications can include control and data/configuration signals that can be communicated by the test controller 510. The test controller can communicate with cluster 0520. Cluster 0520 can communicate with its neighbors to the east, cluster 1522, and north, cluster 2524, since cluster 0 is the southwestern-most cluster. Cluster 1522 can communicate with its neighbor clusters (not shown) by communicating control and data/configuration signals. Cluster 2524 can communicate with cluster 3526 which is one of its possible neighbors. Control and data/configuration signals can be similarly propagated to other clusters (not shown).
Clusters can operate at a hum frequency. A hum frequency can be a frequency at which multiple clusters within the circuit self-synchronize to each other. The hum generation circuit can be referred to as a fabric. The hum generation fabric can form a clock generation structure. In embodiments, a subset of clusters can participate in the hum. For example, in illustration 500, cluster 0520 and cluster 1522 can comprise subset 530. Thus the effective fabric for certain operations can be smaller than the fully utilized fabric. In such cases, the smaller fabric facilitates power management. In embodiments, a rectangular subset of clusters, such as subset 530, participates. In other embodiments, a square subset of clusters participates. Other participating subsets of clusters within the fabric are also possible.
The subsets of clusters can be defined by loading variables via a serial scan chain (not shown). The variables can be loaded before the chips are started, thus controlling which subset or subsets of clusters will participate in the hum generation fabric. The subset of clusters uses less power than the whole fabric of clusters, which can be very valuable for managing power distribution, packaging noise, thermal dissipation and cooling, simultaneous switching noise, software program interfaces, and the like. In some embodiments, the configuration is dynamically changed during runtime. The scan chains can be loaded with zones of subsets of clusters. The zones represent various subsets of clusters that can be used for various operations. A configuration scan chain can be loaded with the contents of the previous scan chain. The operation of a subset of clusters can then be suspended, and the configuration scan chain can then be loaded with the contents of the initial scan chain. Thus the cluster can be configured at the speed of the hum fabric without huge latencies to reconfigure the zones of subsets of clusters. In yet further embodiments, the suspension of operations is pended until the next instruction 0 is encountered. In this way, the process is waiting until instruction 0 is encountered and the elements of the clusters used for the next fabric operation can be included with, or excluded from, as the case may be, a new subset of clusters.
The reconfigurable fabric can include operational states. The fabric can be in only one of a limited number of states, where the states can include temporary states and where the transition from the temporary state can be automatic. Other transitions from a state can require that an internal or an external event occur in order for the transition to be executed. The operational states can include power off, power stabilize, power good, hum clocks stabilize, configured, and so on. Other states can also be included. The operational states can be formed into groups, where the groups can include a cold boot process 600 and runtime active states 602.
The cold boot process begins from power off 610. Power can be applied the fabric, where the application of power can include ramping the power. The power can stabilize 615. Free-running oscillators that generate hum clocks can be running although not yet synchronized. A power good 620 state can be reached. Hum stabilize 625 can occur after a time period. The time period can be based on a system timer. Hum good 630 can occur when the timer has expired. With hum good asserted, a reset signal can be deasserted. The deassertion of reset signal can be indicative of a reset release 635 state being reached. The fabric can be configured 640. Configuration can occur at boot time and can include setting default routing paths, setting cluster identifications (IDs), setting a counter reset value, etc. Program counters (PC's) can be synchronized 645. Program counters across the entire fabric can be synchronized 650 and can begin executing at PC zero. With the fabric synchronized, the fabric can be programmed. Programming can include writing all instructions to the fabric. Programming can include initialization of processing element registers, memories, etc. Programming can conclude with reaching the programmed state 655. Completion of programming can assert an execute starting signal 660.
Runtime active states 602 can result from initializing and programming the fabric. The fabric can remain in a halted state 670 with switches and direct memory access (DMA) active. Further programming can occur. In order to execute processing element instructions, a propagated global signal run starting 675 can be sent to begin executing instructions starting at program counter (PC) zero. Executing instructions can include the run state 680. Occurrence of an external halt signal or an internal halt can cause the fabric to enter a run stopping 685 state. Processing elements can stop executing instructions. Stepping 665 can occur as part of a debugging technique. Various embodiments of the flow 600 and the flow 602 may be included in a computer program product embodied in a non-transitory computer readable medium that includes code executable by one or more processors.
To propagate global signals across the reconfigurable fabric, each propagated global signal originates as an event. To propagate the global signals, a propagator can be used to rebroadcast any timed global signal that is received by the propagator. Each propagator can: contain a programmed value indicating its Manhattan distance from cluster zero; receive a signal assertion as input from one or more cardinal directions (north, south, east, or west); contain a countdown register, loaded with a reset value upon assertion of a signal input, where the reset value can be a function of its Manhattan distance value and a maximum value distance; ignore the assertion of any other propagated global signal when a countdown is currently in progress; and act upon the signal's meaning only when the countdown register reaches zero.
A timed global signal can be asserted in the southwestern-most propagator 700. The southwestern-most corner can have a Manhattan distance of 1 from the origin cluster, cluster zero. Since the northeastern-most corner is an additional 4 steps using Manhattan distance, then the count in the southwestern-most corner is 5. The counts and distances for the remaining cells can be calculated. Note that the counts and distances are equal along diagonals from northwest to southeast because the cells along the diagonals are equidistant from the southwestern-most cell in a Manhattan distance sense. As propagation proceeds, the count in the southwestern-most cell is decremented by 1, making the count equal for the southwestern-most cell and its adjacent diagonal 702. Propagation continues, and the counts are decremented from 4 s to 3 s 704. Propagation continues until the counts in all cells are zero.
The output 842 of the representative circuit 2822 also feeds into the alignment circuit 830, and the output 844 of the representative circuit 3824 also feeds into the alignment circuit 830. Note that while three representative circuits are shown in the diagram 800, in practice, more or fewer than three representative circuits can be used. The alignment circuit 830 serves as a first level alignment circuit (first edge aligner). The diagram 800 includes a first edge aligner combining results from the first plurality of representative logic circuits. As each representative circuit (820, 822, and 824) completes, its corresponding output (840, 842, and 844) is asserted. The diagram 800 includes an output from the first edge aligner that becomes active based on a longest delay path from the first plurality of representative logic circuits. Thus, when all outputs are asserted, the output of the alignment circuit 830 is asserted, serving as a first synchronization signal which is provided to the reset logic 812 as a derived signal 846, and is also sent to a second level alignment circuit as an alignment signal 832. In some cases, the derived signal 846 and the alignment signal 832 are the same signal. In other cases, the derived signal 846 can be a delayed version of the alignment signal 832. The alignment signal 832 can be used as a clock type signal for certain types of logic. In some embodiments, the first plurality of representative logic circuits is comprised of self-resetting logic circuitry and there is no specific reset logic 812 external to the representative circuits themselves.
The reset logic 812 can include some delay so that the representative circuits are reset at some period of time after the signal 846 becomes active. In some embodiments, the delay is a separate circuit from the reset logic 812 itself. The diagram 800 includes a first synchronization signal derived from the results from the first plurality of representative logic circuits. The output 832 of the alignment circuit 830 feeds into the reset logic 812 and also feeds to a second level alignment that is interconnected to multiple clusters, which will be shown further in
The schematic 900 includes another first level alignment circuit 940 that combines results from a second plurality of representative logic circuits (not shown). The schematic 900 includes yet another first level alignment circuit 950 combining results from a third plurality of representative logic circuits (not shown). Each first level alignment circuit, or aligner, (920, 940, and 950) can be disposed within a different cluster. An output of each cluster can be captured by edge capture circuits. The schematic 900 includes an edge capture circuit 970 to capture an output signal 942 from the first level alignment circuit 940, an edge capture circuit 972 to capture an output signal 952 from the first level alignment circuit 950, and an edge capture circuit 974 to capture an output signal 922 from the first level alignment circuit 920. The edge capture circuits capture an edge from their respective incoming signals and retain a consistent output until the edge capture circuit is reset. In this manner, the first level alignment signal can be reset but the edge capture circuit output is held active until its value is used by a second level alignment circuit. The edge capture circuit can include a latch, a flip-flop, a storage element, and so on. The edge capture circuit can capture a rising edge of a signal, a falling edge of a signal, a signal transition, etc. The capture circuit can be used to capture a first or other edge of a signal. In embodiments, the outputs from the first level alignment circuits are also used for reset purposes, self-timing purposes, and so on. In embodiments, the edge capture circuits capture results from the first level alignment circuits and hold the results until the second level alignment circuit can use the results from all of the first level alignment circuits. The output 922 of the first level aligner 920 can be configured to activate a reset circuit 912. The reset circuit 912 places each representative circuit (914 and 916) into an initial state. Similarly, the output 942 of the first level alignment circuit 940 can activate a reset circuit within its respective cluster, and the output 952 of the first level alignment circuit 950 can activate a reset circuit within its respective cluster.
Each edge capture circuit can be coupled to second a level alignment circuit 930. The output from the edge capture circuit 974 can be coupled to the second level alignment circuit 930. The output from the edge capture circuit 972 can be coupled to the second level alignment circuit 930. The output from the edge capture circuit 970 can be coupled to the second level alignment circuit 930. While the outputs from three edge capture circuits are shown, in practice one or more outputs from edge capture circuits can be coupled to a second level alignment circuit.
The output of the second level alignment circuit 930 can be a second level synchronization signal 932 that can trigger the enable circuit 913 of the timing circuit 910. The enable circuit 913 can assert a signal that can allow the representative circuit 914 and the representative circuit 916 to begin operation, starting from the initial state caused by the reset circuit 912. Similarly, the second level synchronization signal 932 can be connected to an enable circuit like the enable circuit 913 in the other clusters to which it is coupled. Each cluster can include a timing circuit similar to the timing circuit 910. In embodiments, the enable circuit 913 is configured to de-assert after a predetermined time interval, such that the enable signal may de-assert prior to the next tic. In some embodiments, the second level synchronization signal 932 can be used to generate a reset signal as well for the representative logic circuits. In this situation, the reset circuit 912 is coupled to the second level synchronization signal 932 rather than the output 922 of the first level aligner 920.
The output 932 of the second level alignment circuit 930 can be coupled to a delay 960. The delay can be a circuit that can be based on a specific time delay. The output 962 of the delay 960 can be configured to activate a reset of the one or more edge capture circuits. As seen in the schematic 900, the signal 962 can reset the edge capture circuits 970, 972, and 974. The reset signal 962 can place each edge capture circuit 970, 972, and 974 into an initial state. In embodiments, the reset signal 962 is the same as the other reset signals 964 and 966 for the other edge capture latches. The initial states of the edge capture circuits can set up these circuits to capture edges (e.g. rising edges) of signals from the plurality of first level alignment circuits. The second level synchronization signal 932 can be used as a clock type signal for certain types of logic.
A circular buffer 1010 feeds a processing element 1030. A second circular buffer 1012 feeds another processing element 1032. A third circular buffer 1014 feeds another processing element 1034. A fourth circular buffer 1016 feeds another processing element 1036. The four processing elements 1030, 1032, 1034, and 1036 can represent a quad of processing elements. In embodiments, the processing elements 1030, 1032, 1034, and 1036 are controlled by instructions received from the circular buffers 1010, 1012, 1014, and 1016. The circular buffers can be implemented using feedback paths 1040, 1042, 1044, and 1046, respectively. In embodiments, the circular buffer can control the passing of data to a quad of processing elements through switching elements, where each of the quad of processing elements is controlled by four other circular buffers (as shown in the circular buffers 1010, 1012, 1014, and 1016) and where data is passed back through the switching elements from the quad of processing elements where the switching elements are again controlled by the main circular buffer. In embodiments, a program counter 1020 is configured to point to the current instruction within a circular buffer. In embodiments with a configured program counter, the contents of the circular buffer are not shifted or copied to new locations on each instruction cycle. Rather, the program counter 1020 is incremented in each cycle to point to a new location in the circular buffer. The circular buffers 1010, 1012, 1014, and 1016 can contain instructions for the processing elements. The instructions can include, but are not limited to, move instructions, skip instructions, logical AND instructions, logical AND-Invert (e.g. ANDI) instructions, logical OR instructions, mathematical ADD instructions, shift instructions, sleep instructions, and so on. A sleep instruction can be usefully employed in numerous situations. The sleep state can be entered by an instruction within one of the processing elements. One or more of the processing elements can be in a sleep state at any given time. In some embodiments, a “skip” can be performed on an instruction and the instruction in the circular buffer can be ignored and the corresponding operation not performed.
The plurality of circular buffers can have differing lengths. That is, the plurality of circular buffers can comprise circular buffers of differing sizes. In embodiments, the circular buffers 1010 and 1012 have a length of 128 instructions, the circular buffer 1014 has a length of 64 instructions, and the circular buffer 1016 has a length of 32 instructions, but other circular buffer lengths are also possible, and in some embodiments, all buffers have the same length. The plurality of circular buffers that have differing lengths can resynchronize with a zeroth pipeline stage for each of the plurality of circular buffers. The circular buffers of differing sizes can restart at a same time step. In other embodiments, the plurality of circular buffers includes a first circular buffer repeating at one frequency and a second circular buffer repeating at a second frequency. In this situation, the first circular buffer is of one length. When the first circular buffer finishes through a loop, it can restart operation at the beginning, even though the second, longer circular buffer has not yet completed its operations. When the second circular buffer reaches completion of its loop of operations, the second circular buffer can restart operations from its beginning.
As can be seen in
Integrated circuit information, cluster information, and cluster distance information can be stored in a cluster distance information store 1120. An obtaining component 1130 can obtain information on logical distances between circuits on a semiconductor chip. The distances can be Manhattan distances (steps north, south, east, and west) from an origin. A determining component 1140 can determine a plurality of clusters within the circuits on the semiconductor chip, wherein a cluster within the plurality of clusters is synchronized to a tic cycle boundary. A tic boundary can be a clock tick, a chip step, a system step, an instruction and so on. An evaluating module 1150 can evaluate a tic cycle count separation across the plurality of clusters using the information on the logical distances. A calculating component 1160 can calculate a plurality of counter initializations wherein the counter initializations compensate for the tic cycle count separation across the plurality of clusters. An initializing component 1170 can initialize a plurality of counters, with a counter from the plurality of counters being associated with each cluster from the plurality of clusters, wherein the counters from the plurality of counters are distributed across the plurality of clusters, and wherein the initializing is based on the counter initializations that were calculated. A starting component 1180 can start the plurality of counters to coordinate calculation across the plurality of clusters.
In embodiments, a computer program product embodied in a non-transitory computer readable medium for circuit synchronization comprising code which causes one or more processors to perform operations of: obtaining information on logical distances between circuits on a semiconductor chip; determining a plurality of clusters within the circuits on the semiconductor chip, wherein a cluster within the plurality of clusters is synchronized to a tic cycle boundary; evaluating a tic cycle count separation across the plurality of clusters using the information on the logical distances; calculating a plurality of counter initializations wherein the counter initializations compensate for the tic cycle count separation across the plurality of clusters; initializing a plurality of counters, with a counter from the plurality of counters being associated with each cluster from the plurality of clusters, wherein the counters from the plurality of counters are distributed across the plurality of clusters, and wherein the initializing is based on the counter initializations that were calculated; and starting the plurality of counters to coordinate calculation across the plurality of clusters.
Each of the above methods may be executed on one or more processors on one or more computer systems. Embodiments may include various forms of distributed computing, client/server computing, and cloud based computing. Further, it will be understood that the depicted steps or boxes contained in this disclosure's flow charts are solely illustrative and explanatory. The steps may be modified, omitted, repeated, or re-ordered without departing from the scope of this disclosure. Further, each step may contain one or more sub-steps. While the foregoing drawings and description set forth functional aspects of the disclosed systems, no particular implementation or arrangement of software and/or hardware should be inferred from these descriptions unless explicitly stated or otherwise clear from the context. All such arrangements of software and/or hardware are intended to fall within the scope of this disclosure.
The block diagrams and flowchart illustrations depict methods, apparatus, systems, and computer program products. The elements and combinations of elements in the block diagrams and flow diagrams, show functions, steps, or groups of steps of the methods, apparatus, systems, computer program products and/or computer-implemented methods. Any and all such functions—generally referred to herein as a “circuit,” “module,” or “system”—may be implemented by computer program instructions, by special-purpose hardware-based computer systems, by combinations of special purpose hardware and computer instructions, by combinations of general purpose hardware and computer instructions, and so on.
A programmable apparatus which executes any of the above-mentioned computer program products or computer-implemented methods may include one or more microprocessors, microcontrollers, embedded microcontrollers, programmable digital signal processors, programmable devices, programmable gate arrays, programmable array logic, memory devices, application specific integrated circuits, or the like. Each may be suitably employed or configured to process computer program instructions, execute computer logic, store computer data, and so on.
It will be understood that a computer may include a computer program product from a computer-readable storage medium and that this medium may be internal or external, removable and replaceable, or fixed. In addition, a computer may include a Basic Input/Output System (BIOS), firmware, an operating system, a database, or the like that may include, interface with, or support the software and hardware described herein.
Embodiments of the present invention are neither limited to conventional computer applications nor the programmable apparatus that run them. To illustrate: the embodiments of the presently claimed invention could include an optical computer, quantum computer, analog computer, or the like. A computer program may be loaded onto a computer to produce a particular machine that may perform any and all of the depicted functions. This particular machine provides a technique for carrying out any and all of the depicted functions.
Any combination of one or more computer readable media may be utilized including but not limited to: a non-transitory computer readable medium for storage; an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor computer readable storage medium or any suitable combination of the foregoing; a portable computer diskette; a hard disk; a random access memory (RAM); a read-only memory (ROM), an erasable programmable read-only memory (EPROM, Flash, MRAM, FeRAM, or phase change memory); an optical fiber; a portable compact disc; an optical storage device; a magnetic storage device; or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device.
It will be appreciated that computer program instructions may include computer executable code. A variety of languages for expressing computer program instructions may include without limitation C, C++, Java, JavaScript™, ActionScript™, assembly language, Lisp, Perl, Tcl, Python, Ruby, hardware description languages, database programming languages, functional programming languages, imperative programming languages, and so on. In embodiments, computer program instructions may be stored, compiled, or interpreted to run on a computer, a programmable data processing apparatus, a heterogeneous combination of processors or processor architectures, and so on. Without limitation, embodiments of the present invention may take the form of web-based computer software, which includes client/server software, software-as-a-service, peer-to-peer software, or the like.
In embodiments, a computer may enable execution of computer program instructions including multiple programs or threads. The multiple programs or threads may be processed approximately simultaneously to enhance utilization of the processor and to facilitate substantially simultaneous functions. By way of implementation, any and all methods, program codes, program instructions, and the like described herein may be implemented in one or more threads which may in turn spawn other threads, which may themselves have priorities associated with them. In some embodiments, a computer may process these threads based on priority or other order.
Unless explicitly stated or otherwise clear from the context, the verbs “execute” and “process” may be used interchangeably to indicate execute, process, interpret, compile, assemble, link, load, or a combination of the foregoing. Therefore, embodiments that execute or process computer program instructions, computer-executable code, or the like may act upon the instructions or code in any and all of the ways described. Further, the method steps shown are intended to include any suitable method of causing one or more parties or entities to perform the steps. The parties performing a step, or portion of a step, need not be located within a particular geographic location or country boundary. For instance, if an entity located within the United States causes a method step, or portion thereof, to be performed outside of the United States then the method is considered to be performed in the United States by virtue of the causal entity.
While the invention has been disclosed in connection with preferred embodiments shown and described in detail, various modifications and improvements thereon will become apparent to those skilled in the art. Accordingly, the forgoing examples should not limit the spirit and scope of the present invention; rather it should be understood in the broadest sense allowable by law.
This application claims the benefit of U.S. provisional patent application “Program Counter Alignment across a Reconfigurable Hum Fabric” Ser. No. 62/399,745, filed Sep. 26, 2016. This application is also a continuation in part of U.S. patent application “Hum Generation Using Representative Circuitry” Ser. No. 15/475,411, filed Mar. 31, 2017, which claims the benefit of U.S. provisional patent application “Hum Generation Using Representative Circuitry” Ser. No. 62/315,779, filed Mar. 31, 2016. Each of the foregoing applications is hereby incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 62399745 | Sep 2016 | US | |
| 62315779 | Mar 2016 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15475411 | Mar 2017 | US |
| Child | 15691254 | US |
