Programmable configuration, level and output voltage range circuits and methods for signal processors

Abstract

A signal processor circuit that buffers a ground-referred, signal-dependent, current. A ground-referred node in the circuit is preferably maintained at a ground level. The ground-referred, signal-dependent, current is preferably buffered such that the ground-referred node is preferably maintained at a ground level independent of changes to the ground-referred, signal-dependent, current.

Description

FIELD OF THE INVENTION

[0002] The present invention relates to a signal processor incorporating digital to analog converters. More particularly, the present invention relates to methods and apparatus for varying the circuit configuration, output voltage range (the difference between the lowest possible output voltage and the highest output voltage) and level (the variance, however small or large, between ground and the lower limit of the output signal range) of such a signal processor.

BACKGROUND OF THE INVENTION

[0003] A digital to analog converter (DAC) converts a digital input word to an analog output. Signal processors which utilize DACs typically operate in either a unipolar or bipolar mode, both of which will be briefly described below.

[0004] The generic equation for determining VOUT in unipolar and bipolar signal processor is shown in Equation 1: 1$\begin{array}{cc}{V}_{\mathrm{OUT}}=G*V_{\mathrm{REF}}*\left(\mathrm{K1}*\frac{\mathrm{INPUT}\mathrm{CODE}}{\mathrm{MAX}\mathrm{INPUT}\mathrm{CODE}}-\mathrm{K2}\right)& \left(1\right)\end{array}$

[0005] where MAX INPUT CODE is the maximum value of INPUT CODE or 2n−1, when INPUT CODE is an n-bit digital word, G is the gain of the signal processor and K1 and K2 are constants that determine the configuration mode. In the unipolar mode configuration (e.g., when the output voltage varies from 0 volts to 5 volts or from 2.5 volts to 7.5 volts) K1=1 and K2=0 so that VOUT varies between 0 and |G*VREF|. In the bipolar mode configuration (e.g., output voltage varies from −5 volts to 5 volts, K1=2 and K2=1 so that VOUT varies between ±G*VREF.

[0006] FIG. 1 shows an example of a previously known unipolar signal processor 10, which receives an input voltage VREF, control signal UPDATE and INPUT CODE, and generates analog output VOUT. INPUT CODE typically is an n-bit digital word that signal processor 10 uses to convert digital input voltage VREF to analog output VOUT. UPDATE is a binary input signal which determines when the INPUT CODE can be used to convert VREF to produce a new VOUT. When UPDATE is LOW, VOUT remains substantially constant. When UPDATE changes from LOW to HIGH, DAC 10 converts VREF to analog output VOUT based on the INPUT CODE.

[0007] Signal processor 10 includes current converter (DAC) stage 12, op-amp 22, capacitor 24 feedback resistor 20 and switch-resistance compensation element SF. Current converter stage 12 includes R-2R ladder 14, switches 161 to 16n and latch and decoder 18 and switch-resistance compensation element ST.

[0008] The R-2R ladder 14 is coupled between VREF and switches 161 to 16n and includes n branches each containing a resistor 25i and a termination branch having resistor 27 and switch-resistance compensation element ST. The R-2R ladder 14 includes a resistor 23 between the top nodes of each branch. Typically, resistors 25 are twice as large as resistors 23. Termination branch resistor 27 is of the same value as resistors 25i. Switch-resistance compensation element ST of the termination branch is connected to GROUND. Resistor 27 and switch-resistance compensation element ST of the termination branch serve to balance the impedance of the R-2R ladder 14 at each top node. Without the termination branch, the current flowing through each branch would differ and thereby cause errors in the current conversion process.

[0009] The INPUT CODE in combination with the reference voltage causes an intermediate current, IDAC to flow according to Equation 2, R is the input impedance of the R-2R ladder: 2$\begin{array}{cc}{I}_{\mathrm{DAC}}=\left(\frac{V_{\mathrm{REF}}}{R}\right)*\left(\frac{\mathrm{INPUT}\mathrm{CODE}}{\mathrm{MAX}\mathrm{INPUT}\mathrm{CODE}}\right)& \left(2\right)\end{array}$

[0010] Feedback resistor 20, feedback switch-resistance compensation element SF, op-amp 22 and capacitor 24 form a current to voltage converter. The op-amp 22 has an inverting input (−) coupled to current converter 12, feedback resistor 20 and capacitor 24, a non-inverting input (+) coupled to GROUND, and an output coupled to VOUT. Capacitor 24 is coupled between inverting input (−) and VOUT to provide a first feedback loop around the op-amp 22. This first feedback loop is not required for operation. Feedback resistor 20 and switch-resistance element SF are coupled between inverting input (−) and VOUT to provide a second feedback loop around the op-amp 22. Switch-resistance compensation element SF, like switch-resistance compensation element ST, is required for matching of the on-resistance of switches 16i from the R-2R ladder 14.

[0011] The current to voltage converter operates to convert intermediate current IDAC to the output voltage VOUT. The resulting, VOUT is shown in Equation 3: 3$\begin{array}{cc}{V}_{\mathrm{OUT}}=-I_{\mathrm{DAC}}*R=-V_{\mathrm{REF}}*\left(\frac{\mathrm{INPUT}\mathrm{CODE}}{\mathrm{MAX}\mathrm{INPUT}\mathrm{CODE}}\right)& \left(3\right)\end{array}$

[0012] FIG. 2 shows a bipolar signal processor 30 which includes circuit 14, comprising an inverting amplifier 40 and gain resistors 42 and 44 coupled between VREF, and current converter 12. Amplifier 40 and gain resistors 42 and 44 serve to invert input voltage VREF. Inverted VREF (i.e., −VREF) is used to generate IREF, as described above in FIG. 1. Alternatively, amplifier 40 and resistors 42 and 44 could be located external to signal processor 30 in the signal path.

[0013] VREF is also coupled to level resistor 38, which is then coupled to the inverting input of op-amp 22 via switch-resistance compensation element So. Capacitor 24 and feedback resistor 36 are coupled between inverting input (−) and VOUT, to provide first and second feedback loops, respectively, around op-amp 22. This is one technique for applying opposite polarity to the current converter and to the level circuitry, a condition which is required for operation of the DAC. However, other suitable techniques for establishing this condition are well-known in the art. Switch-resistance compensation elements So and SF are included in the circuit to match the impedance of the resistors and switches in the R-2R ladder 14 described above in FIG. 1.

[0014] A first signal path from VREF to VOUT via level resistor 38, feedback resistor 36 and op-amp 22, inverts the input signal VREF at VOUT. A second signal path from VREF to VOUT via gain resistors 42, 44, inverting amplifier 40, current converter 12 and op-amp 22, produces the voltage shown in Equation 4 at VOUT: 4$\begin{array}{cc}V=-I_{\mathrm{DAC}}*2R& \left(4\right)\end{array}$

[0015] where IDAC is defined by Equation 2. The total output voltage at VOUT is the combination of the voltage from the first and second signal paths and is shown in Equation 5: 5$\begin{array}{cc}{V}_{\mathrm{OUT}}=V_{\mathrm{REF}}*\left\{2*\frac{\left\{\mathrm{INPUT}\mathrm{CODE}\right\}}{\mathrm{MAX}\mathrm{INPUT}\mathrm{CODE}}-1\right\}& \left(5\right)\end{array}$

[0016] Equation 5 equals the desired result of the voltage conversion shown in Equation 1 for a bipolar configuration where K1=2, K2=1 and G=1. Thus, for a 10 volt input (VREF=10) , the first signal path yields a voltage of −10 volts, while the second signal path provides a voltage between 0 and 20 volts based on the INPUT CODE so that VOUT has a range of ±10 volts.

[0017] The prior art consists of various configurations of signal processor 10 and/or signal processor 30 from FIGS. 1 and 2 in monolithic or discrete form. The configuration was typically chosen to be unipolar or bipolar only and connected permanently as such. To make the configuration switchable between unipolar and bipolar modes, however, extra discrete switches and operational amplifiers have been added, as shown in FIG. 3.

[0018] In FIG. 3, non-inverting amplifier 52 and switch 56 are connected to the signal processor 30 from FIG. 2. Amplifier 52 has inverting input (−) and its output coupled to resistor 38 and noninverting input (+) coupled to switch 56. Switch 56 is provided to couple noninverting input (+) to either VREF or VOUT based on an external logic signal. The signal processor in FIG. 3 operates in unipolar mode when switch 56 connects noninverting input(+) of amplifier 52 to VOUT and operates in bipolar mode when switch 56 connects noninverting input (+) of amplifier 52 to VREF. Otherwise the signal processor in FIG. 3 operates in essentially the same manner as those described above in FIGS. 1 and 2 based on the selected mode. The additional external op-amp 52 (and switch 56) adds an offset and, as such, may provide less than optimum dc performance of the signal processor.

[0019] Additionally, the ac performance of the signal processor is not optimum due to the finite bandwidth and slew rate of this op amp. A specific implementation of the circuit shown in FIG. 3 is shown in the data sheet for LTC 1597 produced by Linear Technology Corporation of Milpitas, Calif.

SUMMARY OF THE INVENTION

[0020] Accordingly, it is the object of this invention to provide methods and apparatus for varying the circuit configuration, output voltage range and level of a signal processor in a monolithic solution without the need to add substantial external circuitry, complexity and cost.

[0021] The signal processor of the present invention includes a converter circuit and utilizes resistors (or other suitable impedance elements) and programmable switches to control whether the signal processor operates in unipolar or bipolar mode, to set the output voltage range, the level of the circuit and/or to provide an asymmetrical range for output signal. Sets of resistors and programmable switches are preferably provided in a level resistor circuit and/or a feedback resistor circuit to enable the invention.

[0022] In an alternative embodiment a signal processor that receives an input signal, a first control word and a second control word, and provides an output signal is provided. The signal processor includes at least two control elements, each of which receives an input signal and a control word and provides a respective intermediate signal. The input signal for one of the control elements is the output signal of the signal processor. This embodiment of the signal processor also includes a summing element that receives a combination of the intermediate signals such that the level, linearity or output signal range of the output signal are programmable based on the control words.

[0023] In one embodiment, the signal processor can include a programmable level circuit which functions as a third control element, receives an additional digital word, and preferably serves to adjust the level of the circuit.

[0024] Additionally, the present invention can preferably use a single reference voltage to provide an asymmetrical output range by selecting the appropriate resistor and switch combination for the level and feedback resistor circuits.

[0025] The present invention also provides for a method of varying the configuration, output voltage range or level of a signal processor. The method determines the mode of operation of the circuit (e.g., unipolar or bipolar), the output voltage range or the level of output signal using programmable switches

[0026] Another embodiment of the invention is a signal processor circuit that receives an input signal and produces an output signal based on the input signal.

[0027] The signal processor circuit preferably includes at least one processing element that is adapted to perform a process on the input signal in order to produce the output signal. The signal processor circuit preferably provides a signal- dependent current.

[0028] The signal processor circuit preferably also includes a signal level node and a buffer coupled between the processing element and the signal level node. The buffer buffers the signal level node from the signal dependent current.

BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Further features of the invention, its nature and numberous advantages will be more apparent from the following detailed description of the preferred embodiments, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:

[0030] FIG. 1 illustrates a conventional unipolar signal processor;

[0031] FIG. 2 illustrates a conventional bipolar signal processor;

[0032] FIG. 3 illustrates a conventional configurable signal processor using discrete components;

[0033] FIG. 4 is a block diagram of a signal processor according to the present invention;

[0034] FIG. 5 is another block diagram of a signal processor according to the present invention;

[0035] FIG. 6 is a specific embodiment of a signal processor according to the present invention;

[0036] FIG. 7 is a table illustrating the effect of various switch configurations on the output voltage of a signal processor according to the invention;

[0037] FIG. 8 is an alternative embodiment of a signal processor according to the present invention;

[0038] FIG. 9 is an alternative embodiment of the signal processor according to the present invention;

[0039] FIG. 10 is a table illustrating the effect of various switch configurations on the output voltage of a signal processor according to the invention;

[0040] FIG. 11 is a specific embodiment of another signal processor according to the present invention; and

[0041] FIG. 12 is another block diagram of a signal processor according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0042] FIG. 4 shows a block diagram of a signal processor 90 according to the present invention. The signal processor is composed of control elements 91-94 (the minimum number of control elements is two), which each receive a control word, e.g., a digital word, and an input signal, e.g., a reference signal, respectively. Input signals 81-84 indicate reference signals. Input signal 81 is shown as being the output signal of the signal processor. Thus, control element 91 preferably functions as a programmable feedback element. Input words 85-88 indicate control words or signals. The control elements, including element 91, each produce intermediate outputs 95-98 based on the respective control word and the input signal input to each element (the intermediate outputs can be either voltage or current). The intermediate outputs are then used as inputs to a summing element 99, which produces an output signal 81 representing a sum of all of the intermediate outputs from control elements 91-94.

[0043] In the preferred embodiment of a signal processor according to the invention, the control words can be used to determine the gain, output signal range, level or linearity (e.g., the linearity of the individual digital steps, or the accuracy with respect to ground) of the output signal. For example, signals 81 and 82 can be processed together with control words 85 and 86 to determine the output voltage range, level and linearity of the output signal.

[0044] FIG. 5 shows another block diagram of a signal processor 100 according to the present invention. The signal processor 100 is composed of a converter circuit 101, level circuit 102, feedback circuit 103 and amplifier 104. Feedback circuit 103 and amplifier 104 combine to form output circuit 105. The INPUT signal is received by the converter circuit 101 and, when present, level circuit 102. The converter circuit 101 receives the INPUT signal and adapts it to provide a first intermediate signal to the amplifier 104, which produces the OUTPUT signal. Level circuit 102 may be used to provide a second intermediate signal to amplifier 104, and feedback circuit 103 provides a feedback path for amplifier 104. The signal processor 100 can be programmed by a single control signal. This control signal can include a single digital word including a first control word provided to the converter circuit, a second control word provided to the level circuit (when present) and a third control word provided to the feedback circuit, or three separate digital words (when the level circuit is present) provided to the converter circuit, the level circuit and the feedback circuit. Feedback circuit 103 and amplifier 104 may be considered as the output circuit because the feedback portion provides a feedback path for amplifier 104.

[0045] The converter circuit may preferably work similarly to converter circuit 12 shown in detail in FIG. 1. Generally, the invention provides that the output circuit includes various sets of switches and resistors which can be programmed by a control signal, e.g., a digital word, to modify the output voltage range and level of VOUT using the intermediate signal from the converter circuit 101 and the intermediate signal from level circuit 102. As mentioned above, the various control words may be provided as one or more control signals in either serial or parallel form.

[0046] FIG. 6 shows a signal processor according to the principles of the invention. The converter circuit 201 preferably includes current converter 12, which is used to modify the magnitude of the INPUT signal based on a control signal, e.g., a first digital word, and inverter circuit 15. The converter circuit 201 provides a intermediate signal as an output. In the circuit shown in FIG. 6, this intermediate signal is expressed as a current.

[0047] Current converter 12 is preferably a 16-bit current output DAC. The DAC is used to control the output in discreet steps with a digital input word. These DACs are well-known in the art. Examples of these DACs are LTC 1595, 1596, 1597, or 1599, produced by Linear Technology Corporation, of Milpitas, Calif. However, any suitable DAC could be used. Current converter 12 has an equivalent impedance value RDAC. The inverter circuit 15 can be formed of amplifier 40 and gain resistor 42 and 44 which are described above. The gain resistors 42 and 44 can be replaced with a series of programmable switches and resistors (not shown) to modify the magnitude of the INPUT signal. These modifications should preferably be made in the same manner as described below in detail with respect to the level and feedback circuits.

[0048] Signal processor 200 also includes resistors 211-215, switches 231-234 and decoders 66 and 67, to allow for the programmability of the configuration, output voltage range and level of the circuit, as will be explained.

[0049] Resistors 211, 212 and switches 231, 232 form programmable level resistor circuit 205 with value RPOFS. Programmable level resistor circuit 205 may preferably be implemented to provide a second intermediate signal to the output circuitry.

[0050] Resistors 213-15 and switches 233-234 form programmable feedback resistor circuit 206 with value RPFB. Resistor circuits 205 and 206 of FIG. 6 can preferably be configured using a single control signal. Resistor 215 and switch-resistance compensation element 235 provide feedback around amplifier 204. Resistors 215 and switch-compensation element 235 can be omitted if at least one of switches 233, 234 is coupled to the inverting input of amplifier 204. Programmable feedback resistor circuit 206 provides a feedback path for amplifier 204. Amplifier 204 and feedback resistor circuit 206 form the output circuit of signal processor 200.

[0051] In the embodiment of the invention shown in FIG. 6, resistor 211 and 212 have value 4R and resistors 213, 214 and 215 have values 2R, 4R and 4R respectively. Thus, feedback resistor circuit 206 can assume one of four values: RPFB=R, 4/3R, 2R, and 4R.

[0052] R represents the unit impedance for this circuit (such as a resistance or other suitable impedance). This unit impedance can be formed by a single resistor or by a complex combination of resistors, as is well known in the art. The remaining resistors can then be ratioed to the unit resistance as additional individual resistors, or also in complex combinations.

[0053] The switches have ON-resistances which preferably are much smaller in value than the individual resistors to which they are coupled. The switches are scaled so the ratio between the switch ON-resistances is the same as the ratio between the associated resistors. Hence the combined impedance value of resistor plus switch ON-resistance for each branch remains precisely ratioed over temperature and supply variations. A multiple NMOS switch combination is the preferred switch implementation. However, other suitable switches may also be used. As with the resistors, the switches may also be formed from more complex combinations.

[0054] Level resistor circuit 205 can assume one of three values: RPOFS=2R, 4R and infinite. Additional switches and resistors can be added to obtain more programmed values for RPFB and RPOFS as desired or the values of the unit resistors can be changed to provide a different set of values. The output voltage VOUT of signal processor 200 is shown in Equation 6: 6$\begin{array}{cc}{V}_{\mathrm{OUT}}=V_{\mathrm{REF}}*\left(\frac{R_{\mathrm{PFB}}}{R_{\mathrm{DAC}}}*\frac{\mathrm{INPUT}\mathrm{CODE}}{\mathrm{MAX}\mathrm{INPUT}\mathrm{CODE}}-\frac{R_{\mathrm{PFB}}}{R_{\mathrm{POFS}}}\right)& \left(6\right)\end{array}$

[0055] wherein RPFB/RDAC=G*K1 and RPFB/RPOPS=G*K2 from Equation 1. The various combinations of the values RPFB and RPOFS enable the configuration and output voltage range of signal processor 200 to be programmable without the addition of external components.

[0056] Decoder 66 and 67 generate control signals 68-71 adapted from the control signal directed to circuits 205 and 206 to control whether any of switches 231-34 are connected to GROUND or the inverting input (−) of op-amp 22. The control signal input to decoder 66 and 67 can preferably be derived from one set of control bits. However, the control signal can also be input as individual control words, e.g., a second control word and a third control word.

[0057] If both switches 231 and 232 are connected to GROUND, the level resistor circuit 205 has a value of RPOFS=infinite (i.e., open circuit). When RPOFS has an infinite value, the signal processor 200 is configured to be in unipolar mode. For instance, if RPOFS is infinite then RPFB/RPOFS=0 and thus K2 from Equation 1 is 0 which means the circuit operates in unipolar mode. VOUT for operation in unipolar mode is shown in Equation 7: 7$\begin{array}{cc}{V}_{\mathrm{OUT}}=V_{\mathrm{REF}}*\frac{R_{\mathrm{PFB}}}{R_{\mathrm{DAC}}}*\frac{\mathrm{INPUT}\mathrm{CODE}}{\mathrm{MAX}\mathrm{INPUT}\mathrm{CODE}}& \left(7\right)\end{array}$

[0058] where RPFB/RDAC=1, 2 or 4. If any or all of the switches in level resistor circuit 205 are turned ON (connected to inverting input (−) of op-amp 22), then the signal processor will operate in bipolar mode.

[0059] Programmable feedback resistor circuit 206 and capacitor 24 (capacitor 24 is not required for operation of the circuit) provide first and second feedback circuits around op-amp 22. The value of feedback resistor circuit RPFB allows the output voltage range and level of signal processor 200 to be programmed by a digital input from decoder 66. Equation 6 shown above describes the bipolar configuration where RPFB/RPOFS determines the level and RPFB/RDAC determines the output voltage range of the circuit.

[0060] FIG. 7 shows a table with exemplary values for VREF, switches 231-34, RPFB, RPOFS and the resulting mode of operation and output voltage range for a given input voltage. Before analyzing the values in the table in FIG. 7, it should be noted that the level and the output voltage range are opposite polarity signals, and the polarity can be switched such that either one is negative or positive with respect to ground.

[0061] The values in the table correspond to the followings guidelines: when the level is smaller than the output voltage range, the output is bipolar (and can be either symmetric or asymmetric). When the level is zero, the output is unipolar. When the level is greater than the output voltage range, then the output is level-shifted unipolar (not shown in FIG. 7). The level value in symmetrical bipolar range is one half the output voltage range. Finally, the values of the output voltage range and level can cover a relatively large range of values depending on impedance, voltage or current ratios.

[0062] In the table of FIG. 7, switches set to 0 are turned OFF (connected to GROUND) and switches set to 1 are turned ON (coupled to inverting input (−) of op-amp 22). If both switches 231 and 232 are turned OFF, then the configuration is unipolar and the output voltage range, either zero to 5 volts, or zero to 10 volts, is determined by which feedback switches 233 and 234 are turned ON. If each of switches 231 and 232 is turned ON then the configuration is bipolar and the range, which is determined as above, is symmetrical about 0. However, if switch 231 is turned ON, then the configuration is still bipolar, but the output range is asymmetrical about ground. Explanation of the other combinations have been eliminated for the sake of brevity.

[0063] The programmable level resistor circuit 205 can be implemented with a level resistor and a switch-resistance compensation element. Alternatively, programmable level resistor circuit 205 could be removed from the circuit to provide a unipolar signal processor with programmable output voltage range. Each alternative uses feedback resistor circuit 206 to program the output voltage range of the circuit.

[0064] Likewise, the programmable feedback resistor circuit 206 can be implemented with a feedback resistor and a switch-compensation element. In this configuration, programmable level resistor circuit 205 enables the mode of the signal processor to be set as either unipolar or bipolar and it also enables the user to provide an asymmetrical output voltage range if more than one set of resistors and switches is used in the level resistor circuit 205. Thus, while the output voltage range in the output is fixed by the value of the feedback resistor, the mode and level remains programmable in this configuration. In addition, even though the feedback circuit is fixed, it is possible to program the output voltage range by providing programmable gain to inverter circuit 15.

[0065] An alternative embodiment of the invention is shown in FIG. 8 in which the first intermediate signal transmitted to the output circuit is a voltage. This is accomplished by using a non-inverting amplifier 304 in the signal path, as will be explained.

[0066] In signal processor 300, input voltage VREF is coupled to converter circuit 301 and level resistor circuit 315. Converter circuit 301 includes divider circuit 305 and voltage conversion circuit 306. The divider circuit 305 provides an output to conversion circuit 306, which provides an intermediate voltage output signal to the non-inverting input (+) of op-amp 308. Divider circuit 305 can be used to adjust the magnitude of the input voltage to voltage conversion circuit 306. It is preferably implemented as a resistor divider to reduce the magnitude of the input voltage to voltage conversion circuit 306 by half. The resistor divider of divider circuit 305 can also be programmable to vary the ratio of the resistors and thus the magnitude of the input voltage signal to voltage conversion circuit 306. Alternatively, divider circuit 305 may be omitted resulting in a more limited programmability of level and output voltage range.

[0067] Conversion circuit 306 differs from current converter 12 in that it provides a voltage output instead of a current output as the intermediate signal which is generated based on the input control signal. In FIG. 6, the current IDAC is generated by circuit 201, and then flows through the feedback resistor circuit. In FIG. 8, on the other hand, the inverting input (−) of non-inverting amplifier 308 follows the non-inverting input (+), which, in turn, reflects the voltage at the output of the converter circuit 301. This voltage causes a current to flow in the parallel combination of level circuit 315 and gain circuit 310, which then flows through feedback circuit 320 to generate the output voltage. Gain circuit 310 is necessary to allow programmability of the output voltage range.

[0068] Level circuit 315 is composed of resistors 318, 319 and switches 316, 317 and has value RPOFS, Though the circuit in FIG. 8 shows two sets of resistors and switches in level resistor circuit 315, the number of switches and resistors may be varied to provide different characteristics for the circuit.

[0069] Level circuit 315 operates in the same manner and serves substantially the same function as the level resistor circuit 205 shown in FIG. 6. Thus, when the level value is configured to be smaller than the output voltage range, the signal processor 300 operates in level-shifted unipolar mode. When the level is zero, the signal processor 300 operates in unipolar mode. When the level is greater than the output voltage range, the signal processor 300 operates in leveled unipolar mode.

[0070] Gain circuit 310 includes resistors 313, 314 and switches 311, 312 to provide the resistor value RPG. As above, the number of resistors and switches can be varied and need not be limited to two sets.

[0071] The feedback circuit 320 includes resistors 323, 324 and switches 321, 322 and operates in the same manner as feedback circuit 206 described above in FIG. 6. For example, one of switches 321 and 322 always must be turned ON for the circuit to operate. This can be accomplished by setting one switch to be closed or by using the switch-resistance compensation element. The blocks shown as level circuit 102 and feedback circuit 103 in FIG. 5 would be made up of level circuit 315, gain circuit 310, and feedback circuit 320.

[0072] The equation for the unipolar mode of circuit 300 in FIG. 8 is: 8$\begin{array}{cc}{V}_{\mathrm{OUT}}=V_{\mathrm{REF}}*K*\frac{\mathrm{INPUT}\mathrm{CODE}}{\mathrm{MAX}\mathrm{INPUT}\mathrm{CODE}}\left(1+\frac{R_{\mathrm{PFB}}}{R_{\mathrm{PG}}}\right)& \left(8\right)\end{array}$

[0073] where K is a divider ratio in the converter circuit 301. In unipolar mode, the gain of the circuit in FIG. 8 is determined by the ratio of RPFB to RPG, while the range of VOUT is determined by this gain and any magnitude modification provided in divider circuit 305.

[0074] In bipolar mode, or level-shifted unipolar mode, the output signal level is determined by the ratio of RPFB to RPOPS, while the output signal range is determined by the ratio of RPFB to the parallel combination of RPOPS and RPG. The output signal range is scaled by the divider ratio K. The equation for the bipolar mode and the level-shifted unipolar mode of circuit 300 is: 9$\begin{array}{cc}{V}_{\mathrm{OUT}}=V_{\mathrm{REF}}\left[K*\frac{\mathrm{INPUT}\mathrm{CODE}}{\mathrm{MAX}\mathrm{INPUT}\mathrm{CODE}}\left(1+\frac{R_{\mathrm{PFB}}}{\frac{R_{\mathrm{POFS}}*R_{\mathrm{PG}}}{R_{\mathrm{POFS}}+R_{\mathrm{PG}}}}\right)-\frac{R_{\mathrm{PFB}}}{R_{\mathrm{POFS}}}\right]& \left(9\right)\end{array}$

[0075] The same general conditions described in reference to the circuit and equations of FIG. 6 apply to the circuit described in reference to circuit 300 in FIG. 8. One difference between these circuits is that, in circuit 300, VREF is preferably divided down by voltage divider 305 as described above.

[0076] FIG. 9 shows a specific embodiment of a signal processor according to the principles shown in FIG. 8. In FIG. 9, circuits 305, 306 show one possible example of a configurable input impedance wherein divider circuit 305 is a single resistor and conversion circuit 306 implements a programmable resistor-string DAC. In one configuration, the impedance value of resistor 830 equals the impedance value of resistor 840. This results in K=0.5.

[0077] FIG. 9 also includes an additional resistor and switch in gain circuit 820. This shows the capability of these circuits to increase the number of resistors and switches to further govern the output voltage range and level.

[0078] FIG. 10 shows a table incorporating exemplary values and modes for settings of the circuit shown in FIG. 9.

[0079] FIG. 11 shows the signal processor 1100, similar to signal processor 200 of FIG. 6. Signal processor also includes, however, an additional buffer circuit 1110. One important purpose of the buffer circuit is as follows. It is well known in the art that signal processors, such as signal processor 200, contain a signal level, preferably ground, to which all other signals are referred. This system ground level may receive signal-referred—e.g., ground-referred—signal-dependent current. Signal-referred, signal-dependent current is current that flows to a node at which the signal level is maintained, preferably at a ground potential, and that changes based on the magnitude and/or other characteristics of the input or output signal from signal processor 1100. This signal-referred, signal-dependent current may be received from a signal processing portion of the signal processor. Because this current is signal-dependent, as the control words, input signal or output signal changes, the ground level may change.

[0080] When the ground level changes, the current flowing to the ground level changes. When the current flowing to the ground level changes, the signal processor accuracy may be adversely affected.

[0081] In the embodiment of the invention shown in FIG. 11, buffer 1110, which may preferably be implemented as a unity-gain buffer, preferably buffers a ground level node 1120 so that no ground-referred, signal-dependent current flows to the ground level node 1120. Because the ground level node 1120 is buffered from the rest of the circuit, the accuracy of the signal processor 1100 is substantially unaffected and preferably independent of changes to the signal. Furthermore, ground level node 1120 may preferably be maintained at a pre-determined level without substantial change.

[0082] Specifically, current converter 12 may have a complementary current output signal which contains ground-referred, signal-dependent current, as is known in the art. This complementary current output signal should preferably be maintained at the same potential level as ground level node 1120. Also, each of programmable level resistor circuit 205 and programmable feedback resistor circuit 206 may contain signals that need to be maintained at the ground level. These signals may also contain signal dependent current.

[0083] Each of the signals from current converter 12, from programmable level resistor circuit 205 and from programmable feedback resistor circuit 206 are preferably buffered by buffer 1110. Buffer 1110 may preferably divert all of the signal dependent current to its power supplies. Thus, the ground level at ground level node 1120 does not contain signal dependent current and the accuracy of the signal processor is preferably maintained.

[0084] FIG. 12 shows an additional embodiment of a signal processor circuit 1200 according to the invention. In this embodiment, signal processor circuit 1200 includes an additional control element 1210 that preferably is configured to receive the output signal 1224, an additional control word 1222, and that provides an additional intermediate signal 1226. The additional feedback loop adds variability and functionality to the circuit over, for example, the variability and functionality of signal processor 90 shown in FIG. 4. Additional control element 1210 may preferably be implemented in a fashion similar to circuit 206 shown in FIG. 6 or in another suitable fashion.

[0085] Several preferred embodiments are described above. However, persons skilled in the art will appreciate that the present invention can be practiced in embodiments other than those illustrated above, including other known methods of modifying the level and output voltage range of VOUT in signal processing circuits. The present invention is only limited by the claims which follow.

Claims

1. A signal processor circuit that receives an input signal and produces an output signal based on the input signal, the signal processor circuit comprising: at least one processing element that is adapted to perform a process on the input signal in order to produce the output signal, and that provides a signal-dependent current; a signal level node; and a buffer coupled between the processing element and the signal level node that buffers the signal level node from the signal dependent current.

2. The signal processor circuit of claim 1, wherein the buffer is adapted to maintain the signal level node at substantially the same potential independent of a change to the signal-dependent current.

3. The signal processor circuit of claim 1, wherein the signal level node comprises a ground level node.

4. The signal processor circuit of claim 1, wherein the buffer comprises a unity-gain buffer.

5. A method for maintaining a signal level node of a signal processor at a pre-determined level comprising: processing an input signal to provide an output signal; during the processing, providing a signal-dependent, ground-referred current to the signal level node; and maintaining the signal level node at a pre-determined level by buffering the signal-dependent, ground-referred current.

6. The method of claim 5 wherein the processing occurs independent of changes to the signal-dependent, ground-referred current.

7. The method of claim 5 further comprising varying the input signal.

8. The method of claim 5 the processing further comprising varying the output signal based on the input signal.

9. A system for maintaining a signal level node of a signal processor at a pre-determined level comprising: means for processing an input signal to provide an output signal; a means for providing a signal-dependent, ground-referred current to the signal level node during the processing; and a means for buffering the signal-dependent, ground-referred current in order to maintain the signal level node at a pre-determined level.

10. The system of claim 9 wherein the means for processing comprises a means for processing independent of changes to the signal-dependent, ground-referred current.

11. The system of claim 9 the processing further comprising a means for varying the output signal based on the input signal.

12. A signal processor that receives an input signal, a first control word and a second control word, and provides an output signal, comprising: at least two control elements including; a first control element, that receives the first control word and the input signal, that is programmable based on the first control word, and that provides a first intermediate signal, and a second control element, that receives the output signal, that receives the second control word, that is programmable based on the second control word, and that provides a second intermediate signal; and a summing element that receives a combination of the first intermediate signal and the second intermediate signal, and provides the output signal, such that at least one characteristic of the output signal selected from a group consisting of a) a level b) a linearity c) an output signal range d) a combination thereof is programmable based on the first control word and the second control word.

13. The signal processor according to claim 12, the signal processor further comprising a third control element that receives the input signal, that is programmable based on a third control word, that provides a third intermediate signal to the summing element.

14. The signal processor according to claim 13, wherein at least one of a) the impedance value of the first control element b) the impedance value of the second control element c) the impedance value of the third control element and d) a combination thereof determines the mode in which the signal processor operates.

15. The signal processor according to claim 13, wherein the third control element comprises at least one programmable combination of an impedance and a switch, wherein said combination has an impedance value that is defined by controlling the switch.

16. The signal processor according to claim 13, wherein at least one of a) the first control element b) the second control element and c) both the first control element and second control element is a converter circuit including a digital-to-analog converter.

17. The signal processor according to claim 13, wherein the second control element is a programmable feedback circuit that provides a feedback path for the summing element.

18. The signal processor according to claim 13, wherein the summing element includes an amplifier.

19. The signal processor according to claim 13, wherein each of the first control element and second control element includes a plurality of switches and impedances.

20. The signal processor according to claim 13, wherein the signal processor can operate in a mode selected from a group consisting of a) unipolar mode b) bipolar mode and c) level-shifted unipolar mode.

21. The signal processor according to claim 13, wherein at least one of a) the first intermediate signal and b) the second intermediate signal is a current signal.

22. The signal processor according to claim 13, wherein at least one of a) the first intermediate signal and b) the second intermediate signal is a voltage signal.

23. The signal processor according to claim 13, wherein at least one of a) the first control element and b) the second control element comprises at least one programmable combination of an impedance and a switch, wherein said combination has an impedance value that is defined by controlling the switch.

24. A signal processor that receives an input signal, a first control word, a second control word, and a third control word and provides an output signal, comprising: at least three control elements including; a first control element, that receives the first control word and the input signal, that is programmable based on the first control word, and that provides a first intermediate signal; a second control element, that receives the output signal, that is programmable based on the second control word, that receives the second control word, and that provides a second intermediate signal; and a third control element, that receives the output signal, that receives the third control word, that is programmable based on the third control word, and that provides a third intermediate signal; and a summing element that receives a combination of the first intermediate signal, the second intermediate signal, and the third intermediate signal and provides the output signal, such that at least one characteristic of the output signal selected from a group consisting of a) a level b) a linearity c) an output signal range d) a combination thereof is programmable based on the first control word, the second control word, and the third control word.