The disclosed system and method relate to integrated circuits. More specifically, the disclosed system and method relate to integrated circuits including programmable current mirrors.
Current mirrors are widely used in analog circuit design. Simple current mirrors produce an output current (IO) that is related by a ratio to a reference current (IR). The reference current is received by a reference transistor having an associated width-to-length ratio (αR). The gate of the reference transistor is connected to the gate of a mirror transistor having a gate width-to-length ratio (αR). The magnitude of the reference current IR determines the gate voltage arising at the reference transistor, which is passed to the gate of the mirror transistor. The gate voltage of the mirror transistor determines the magnitude of the output current IO drawn by the mirror transistor.
U.S. Pat. No. 6,462,527 issued to Maneatis discloses one example of a conventional programmable current mirror and includes a reference system 48 having a plurality of transistors 50, 52, 54, 56 coupled in parallel, and a mirror system 49 having a plurality of transistors 58, 60, 62 coupled in parallel as illustrated in
Where,
k=μCOX;
COX is the capacitance of the oxide layer of transistor 56;
Vth is the turn-on voltage of transistor 56; and
Thus, if the transistor size in the reference system is changed, the biasing voltage will need to be changed.
Accordingly, an improved programmable current mirror is desirable.
In some embodiments, a programmable current mirror includes a reference transistor, first and second mirror transistors, and a first current bypass. The reference transistor has a source and a gate coupled to a reference current node. The first and second mirror transistors are coupled together in series at a first node. Each of the first and second mirror transistors have gates coupled to each other and to the gate of the reference transistor. The first current bypass includes a switch disposed in parallel with the second mirror transistor. The first current bypass is coupled to a source and a drain of the second mirror transistor and to the first node.
In some embodiments, a programmable current mirror includes a first reference transistor, first, second, third, and fourth mirror transistors coupled in series, and first, second, and third current bypasses coupled in parallel with the second, third, and fourth mirror transistors. The first reference transistor has a source and a gate coupled to a first node for receiving a reference current. The first and second mirror transistors are coupled together at a second node. The second and third mirror transistors are coupled together at a third node. The third and fourth transistors are coupled together at a fourth node. Each of the mirror transistors has a gate coupled together and to the gate of the first reference transistor. Each of the current bypasses includes a switch. The first current bypass is coupled to the second and third nodes in parallel with the second mirror transistor. The second current bypass is coupled to the third and fourth nodes in parallel with the third mirror transistor. The third current bypass is coupled to a source and a drain of the fourth mirror transistor and to the fourth node.
In some embodiments, a programmable current mirror includes a plurality of reference transistors coupled in series and a plurality of mirror transistors coupled in series. Each of the reference transistors has a gate coupled to the gates of the other reference transistors and to a first reference current node. Each of the mirror transistors has a gate coupled to the gates of the other mirror transistors and to the gates of each of the plurality of reference transistor. A respective current bypass is coupled in parallel with each of the reference and mirror transistors. Each of the current bypasses includes a switch.
I
O=(1/n)*IR, 1≦n≦8 Eq. 1
The value of n, which as shown in Equation 1 determines the value of the output current, IO, is determined by the application of a three bit digital control word to open and close switches 212, 214, and 216. Table 1 below illustrates the output current IO with respect to the reference current IR for each of the eight three-bit control words.
Table 1 also demonstrates that the gate-to-source voltage, VGS, for the reference transistor 202 does not change as the digital control word is changed. Accordingly, the programmable current mirror 200B does not require bias adjustments different control settings, e.g., different control words.
Referring now to
The closing of one or more switches 318, 320, and 322 along current bypass 330 and/or the closing of one or more switches 324, 326, and 328 along bypass 332 adjusts the magnitude of the output current IO with respect to the reference current IR. For example, with all of the switches 318-328 in the open position, then the output current IO will be equal to the reference current IR assuming that the transistors 302 and 310 have the same gate width-to-length ratios, αR. Accordingly, closing one or more of the switches will adjust the gate width-to-length ratio of the reference circuit or the mirror circuit and therefore also change the ratio of the output current IO with respect to the reference current IR. The opening and closing of the switches 318-328 may be controlled by a six-bit digital control signal with the first or right-most three bits, e.g., bits B0-B2, respectively controlling the opening and closing of switches 328, 326, and 324, and the fourth through sixth bits, e.g., bits B3-B5, respectively controlling the opening and closing of switches 322, 320, and 318.
The improved programmable current mirror described herein may be incorporated into a phase-locked loop (PLL) circuit for clock generation in a wide range of ASICs including, but not limited to, network controllers, I/O controllers, graphics processors, or the like.
Although the invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments of the invention, which may be made by those skilled in the art without departing from the scope and range of equivalents of the invention.