1. Technical Field
The present invention generally relates to the processing of clock signals and, more particularly, to a programmable delay generator of equal delay steps and a cascaded interpolator.
2. Description of the Related Art
Phase rotators are critical components of clock subsystems of modern data processing and communications systems. Phase rotators are circuits that modify, in a highly precise and reproducible fashion, the phase of clock signals within an unlimited phase range and therefore are capable of generating clock signals with programmable phase and frequency offsets. A very general approach to building phase rotators is to use a two-stage circuit, where the first stage performs generation of a fixed set of clock phases that are uniformly distributed on a phase circle and/or selection of two adjacent phases from such a set, that is followed by the second stage that interpolates between the two selected phases using a high-precision interpolator circuit. The most common way to generate a set of coarse clock phases is to use a Delay Locked Loop (DLL) composed of the required number of identical delay stages, or obtain them using a divider of a higher clock frequency. Interpolation is conventionally done with current-mode logic (CML) mixers driven with current-mode digital-to-analog converters (DACs). While highly linear, CML interpolators have poor compatibility with most recent circuit designs that are predominantly of the CMOS type, i.e., of the type that employ full (rail-to-rail) signal swing and cannot directly use reduced-swing CML clocks.
One can implement an interpolator that is CMOS-compatible by using a combination of two (or more) groups of dotted CMOS tri-state inverters, with each group receiving a common input signal and all groups having one common output. The interpolation weights in this case are simply the numbers of active inverters in each group (a tristate inverter can be either fully on or off). However this method has lower linearity, and its nonlinearity increases with increases of the mutual delay of the clock phases, so it is generally limited to mutual delays of 45 degrees or less. Another disadvantage is the rigid relationship between the interpolation accuracy in bits and the number of inverters present in the circuit, the latter doubling with each extra bit of accuracy. For example, to create one output clock phase with 16 equidistant interpolated states (4 bits of accuracy) one needs at least 32 tri-state inverters for a single-ended output and 64 inverters for a dual-rail output. An immediate consequence of such use of 2^n elements to achieve n-bit accuracy is that such interpolator is natively controlled with a thermometer code. However, a thermometer code uses N−1 bits to represent N states, while binary code uses log 2(N) bits to represent N states.
The large number of coarse clock phases required by CMOS-type interpolators creates another important problem, namely skew introduced by the selection of the coarse phases from a large set, where a skew-free selection of the coarse phases from a large set is desired. However, the skew-free selection of the coarse phases from a large set is challenging due to the significant size of phase-generation circuitry and the generally non-uniform topology of such a selector.
According to an aspect of the present principles, there is provided a programmable delay generator of equal delay steps. The programmable delay generator includes a first delay line and a second delay line. The first delay line has a plurality of stages. Each of the plurality of stages includes a respective delay buffer and has one signal input and one signal output. The second delay line has a plurality of stages equal in number to the plurality of stages of the first delay line. Each of the plurality of stages of the second delay line includes a respective selecting element and has two signal inputs, one select input for selecting one of the two signal inputs, and one signal output. The first delay line and the second delay line are configured in parallel with respect to each other, are interconnected, and have a same signal propagation direction. Each of the delay steps provided by each of the plurality of stages of the second delay line is equal to a difference between a delay through one of the plurality of stages of the first delay line and a delay through one of the plurality of stages of the second delay line.
According to another aspect of the present principles, there is provided a method for programmable delay generation of equal delay steps. The method includes forming a first delay line having a plurality of stages. Each of the plurality of stages includes a respective delay buffer and having one signal input and one signal output. The method further includes forming a second delay line having a plurality of stages equal in number to the plurality of stages of the first delay line. Each of the plurality of stages of the second delay line includes a respective selecting element and has two signal inputs, one select input for selecting one of the two signal inputs, and one signal output. The first delay line and the second delay line are configured in parallel with respect to each other, are interconnected, and have a same signal propagation direction. Each of the delay steps provided by each of the plurality of stages of the second delay line is equal to a difference between a delay through one of the plurality of stages of the first delay line and a delay through one of the plurality of stages of the second delay line.
According to yet another aspect of the present principles, there is provided a cascaded interpolator. The cascaded interpolator includes a plurality of interpolator stages. Each of the plurality of interpolator stages has two signal inputs and two signal outputs, and is configured to receive two input signals having two different phases and to generate therefrom two output signals that have a phase separation equal to a fraction of a phase separation of the two input signals. The cascaded interpolator further includes a phase converter connected to a last stage of the plurality of single-bit interpolator stages. The phase converter is configured to convert the two output signals into a single final output signal of a given phase.
According to still another aspect of the present principles, there is provided a method for cascaded interpolation. The method includes forming a plurality of interpolator stages. Each of the plurality of interpolator stages has two signal inputs and two signal outputs, and is configured to receive two input signals having two different phases and to generate therefrom two output signals that have a phase separation equal to a fraction of a phase separation of the two input signals. The method further includes forming a phase converter connected to a last stage of the plurality of single-bit interpolator stages. The phase converter is configured to convert the two output signals into a single final output signal of a given phase.
These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein:
As noted above, the present principles are directed to programmable delay generator of equal delay steps and a cascaded interpolator. Both the programmable delay generator and the binary encoded cascaded interpolator are implemented as all-CMOS. As used herein, “all-CMOS” refers to a circuit where signals in all points in the circuit have full, rail-to-rail swing.
With respect to one or more embodiments, the present principles aim to create an all-CMOS phase rotator, or elements (e.g., the programmable delay generator and the binary encoded cascaded interpolator) that are capable of being in such a phase rotator, using a novel topology that allows the rotator to merge phase generation and phase selection circuitry into a uniform array of delay stages and switching elements that achieves equidistant separation of the selected phase positions by construction. Moreover, a new topology of the CMOS-type interpolator is introduced that includes a cascade of identical 1-bit sections for significant hardware savings in contrast to conventional thermometer-encoded CMOS interpolators.
Thus, the present principles are directed to an original architecture for an all-CMOS phase rotator, where the architecture can be considered to include two independent components, where each of these components are novel over the prior art. The first component involves the efficient generation of one pair of adjacent clock phases out of a relatively large set of equidistant clock phases (as opposed to a more conventional way to first generate a full set and then to proceed to select just two phases out of that full set). This generation is based on using a uniform array of delay and switching elements that utilizes vernier topology. As used herein, a vernier topology refers to and/or is otherwise directed to, an array where the delay introduced by such array changes in increments equal to a difference between two schematic delays. That is, the delay changes in increments equal to a difference between a signal propagation delay through one stage of a first (main) delay line, and a signal propagation delay through one stage of a second (merging) delay line. The second architecture component involves the use of a multiple stage interpolator that interpolates between the incoming pair of relatively close clock phases using a cascade of identical single-bit sections, each having two inputs and two outputs and one control bit that adds one bit of accuracy to the overall interpolation process. More specifically, each interpolation stage includes a 2:1 MUX and a fixed 1:1 mixer (interpolator). The 2:1 MUX selects one of the two incoming phases as the first output. The fixed 1:1 mixer (interpolator) generates the second output. The last stage in the cascade is terminated with a single 1:1 mixer to produce the final single rotator output. The use of the preceding architecture advantageously results in the situations where, depending on the control bit value in each section, its output pair of phases takes one of two possible configurations, while the spacing between these two phases is reduced by a factor of two.
As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.
Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
Aspects of the present invention are described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The present invention aims at advancing the architecture of phase rotators that use full-swing (rail-to-rail) signaling, also known as CMOS signaling, for reduction of circuit power and area compared to circuits that utilize the more traditional signaling for analog circuits, namely reduced-swing differential signaling which is also known as CML signaling. Regardless of the type of the signaling, the vast majority of phase rotator architectures can be described as a two-stage circuit that employs a coarse stage and a fine stage that it is convenient to illustrate using the specific example in
The DLL 103 is composed of N=6 identical delay stages/elements 111 with controllable delay that is adjusted by the feedback loop 104 to yield an overall phase delay of 180 degrees. Since the delay stages/elements 111 are nominally identical, this phase delay is uniformly distributed between these N elements 111, yielding 180/N=30 degrees of phase delay per each delay element 111. The delay elements 111 are implemented as CML circuits using differential, reduced swing signaling and therefore they automatically provide another 6 complementary phases with a 180 degree shift thus yielding a complete set of 2N=12 clock phases that are uniformly distributed on a phase circle.
The next step within the coarse stage of the rotator 100 shown in
The two adjacent coarse phases, an even and an odd, are then applied to the fine stage which is implemented using a CML interpolator 150 shown in detail in
The interpolation accuracy of CML interpolators similar to that shown in
In contrast to CML interpolators, interpolators using CMOS signaling have generally worse linearity and therefore require a larger number of coarse phases with respectively finer spacing to operate adequately (usually 8 phases or more). As a consequence, in the design of phase rotators using CMOS signaling, larger emphasis is put on the precision of the coarse stage that applies to both coarse phase generation and the subsequent selection for the final coarse output.
The root issue of potential inaccuracies in the output coarse phases (obtained via the aforementioned two-step process involving the generation of a complete phase set followed by the selection of just two of the phases in the set) is that the resulting structure is redundant (most phases are not used at any given moment) and the phase collection network that brings the phases to the phase selection devices often lacks symmetry and/or uniformity. To address this issue, the present principles introduce a new topology for coarse phase generation that is free from these deficiencies. More specifically, the new present principles merge delay generation elements and switching (selection) elements in a uniform array of multiple stages that can directly generate the two output coarse phases (belonging to a large set of equidistant phases) without generating the ones that are not needed.
The all-CMOS phase rotator 200 includes a coarse phase generator/selector 210 corresponding to the coarse stage 298 and a fine phase rotator stage 250 corresponding to the fine stage 299. The fine phase rotator stage 250 includes a fine phase one-bit cascadable interpolation section 251 and a termination stage 260. Hence, the all-CMOS phase rotator 200 of
In the embodiment of
Similar to the rotator 100 of
The two main distinctive features of the new architecture of the coarse rotator stage 298 shown in
The second independent innovation of the new rotator architecture shown in
In order to explain the principles of clock phase transformations as they propagate through the cascade of single-bit interpolators and the final termination stage 260, let us consider a 3 bit fine phase rotator stage.
This completes the architectural description of the new phase rotator, however on the circuit level (not shown in
We will now discuss an implementation of the buffer delay stages of the rotator.
An important observation is that the two inverters of the regular dual-rail buffer in
The basic buffer topology in
The reason for the input phases to be relatively close is to avoid a crow-bar condition between the two buffers. Such condition develops when the mutual delay between the two input phases is sufficiently large to become a significant portion of the output transition time. Consider that before the early clock phase transition there are no currents in the circuit, since all active pull-up and pull-down current sources (i.e. those connected to the outputs via inverters) have reached zero headroom. The inverters receiving the late phase will retain their zero currents as long as the change in the circuit outputs caused by the early-phase inverters action is small to keep the headroom of its current sources in the late-phase ones sufficiently low to prevent them from applying an opposing current to the outputs. This is easily achieved in the new architecture due to its use of the vernier principle that allows one to have relatively slow slew rates in combination with small phase separation that must be a small fraction of the total output transition time, which has a maximum value of one half of the clock period.
The primary reason to use current-limiting devices in the multiplexers 278 used in the rotator 200 shown in
An important shortcoming of the multiplexer 1100 shown in
There are two independent ways to cancel the effect of such capacitive feed-through, both of which are used in the invention. The first way is to add a complete set of four dummy (permanently disabled) tri-state inverters 1211 to the circuit shown in
There is an alternative second way to eliminate the effect of capacitive feed-through by forcing the de-selected clock input to some fixed value that can be achieved by appropriately controlling the circuit that generates it. This second approach essentially shifts the problem from the original multiplexer circuit in
In accordance with the present principles, the first approach (extra dummy tri-state inverters 1211) is used in the fine rotator stage 299, i.e. within the singe-bit interpolators 251. The coarse phase generation stage 298, in contrast, is sensitive to additional increases in delay and/or power, and therefore it employs the second approach.
Let us explain how one can implement the second approach in the coarse rotator stage 298, where the multiplexers 278 are driven by polarity control circuits (XOR) 213 on one input and by delay buffers 277 of the merging delay line 212 on the other input. Feed-through cancellation in this structure is achieved primarily by de-activating (i.e. forcing to a fixed output value) the majority of XOR circuits 213 that connect the unused taps of the main tapped delay line 211 to the multiplexers 278 of the merging delay line 212.
Let us now consider an independent topic of glitchless switching. Generally a glitch within the coarse phase generation stage 298 occurs when a certain multiplexer in the clock path switches between two clock phases that are significantly far apart (e.g. have opposite polarity) and therefore can assume significantly different values at the moment of switching. A particularly dangerous condition occurs at the so-called “stitching region” where the phase at one end of the delay line structure is replaced with the phase at the other end (with change in polarity to compensate for 180 degrees of phase delay along the delay line).
In order to guarantee that phase switching within the coarse phase generator is glitch-free, the following measures are taken: first, XOR cells of all taps except the main tap and two adjacent to it are kept in a disabled state, as explained above. (The main tap is the tap through which the clock is routed on its path from the tapped delay line to the even and odd merging delay lines.) In order for a tap to change polarity it must be de-activated first. Second, the 2:1 multiplexers 278 of the merging delay line 212 are configured so that the multiplexer driven by the main active tap and all multiplexers to the left of it are in the “merging” position (i.e. they accept the signal from their respective taps and disregard the signal from their preceding buffers in the merging delay line), while all multiplexers to the right of it are set in a “propagation” state, i.e. they receive the signal from the preceding buffer in the merging delay line and disregard the tap signal from their respective XOR cell input. The only exception is the leftmost multiplexer (tap 0) that has no left neighbor and hence is permanently wired in the “merge” position. The overall goal of such arrangement is to be always prepared for a tap switching (translation) process by one position in either direction, in a way that such translation of the tap position could be accomplished by switching just one 2:1 multiplexer in the merge delay line 212. More specifically, a move to the left would be accomplished by reversing the select state of the multiplexer of the main tap from merging to propagating, while moving the active tap position by one step to the right is achieved by reversing the select state of the multiplexer to the right from the main one, from propagating to merging.
Besides those primary switching events that directly alter the clock propagation path, one would also need to switch the select state of the peripheral taps to restore the same active tap configuration that is translated by one position to the left or to the right. Such translation simply means de-activation of XOR cell of one tap and activation of XOR cell of another to form a new group of three active taps. These XOR cell switching events however have no direct effect on the main clock propagation path and hence their timing is not critical.
A special case that is handled slightly differently arises near the stitching boundary that involves the taps on the two opposite sides of the coarse delay generator, since those edge positions have only one neighbor tap. In order to make moves of active tap position across the stitching boundary identical to regular ones, the structure uses a redundant tap (numbered 8) that replicates the first tap (numbered 0) in a sense that the two are set exactly 180 degrees apart in phase and are always activated in opposite polarity states, so the clock paths routed through them would result in an identical output (selection of which one is actually routed to the output is determined by the select state of the multiplexer associated with the redundant, 8th tap). With such arrangement when both tap 0 and tap 8 are active, one uses tap 1 as the “right” extra tap, and tap 7 as “left” extra tap of the “three taps active” combination and hence the general rule described in the preceding paragraph for regular (non-boundary) taps seamlessly applies to the redundant boundary tap pair 0,8.
In order to further enhance the glitch suppression capabilities of the coarse phase generator all multiplexers within the merge delay lines are implemented as 1:1 interpolators, i.e. they are made of two identical multiplexer 1100 instances shown in
An additional benefit of using interpolating multiplexers takes place in the redundant (8th) tap which during activation of this tap (as main, center tap) is allowed to assume either one of its two select states, i.e. choose either routing the clock signal through tap 0 (the leftmost) or through tap 8 (the rightmost). In practice, the best position to choose in this case is of constant (non-transitory) 1:1 interpolation between these two paths since it minimizes the error arising from the finite accuracy of setting the delay line to a phase delay of 180 degrees (commonly referred to as “stitching error”). The latter position is easily achievable with the interpolating multiplexer by applying the controls accordingly.
The interpolating multiplexer enables glitchless switching not only in the coarse phase generator, but also in the fine rotator section composed of a cascade of single-bit interpolators. As a diagram of fine rotator states in
Let us consider the structure of a single-bit fine interpolation rotator stage in more detail. While on block diagram such stage is composed of two different devices, a 2:1 multiplexer (with feed-through compensation) and a 1:1 interpolator, in actual implantation both of these devices are made of identical parts, specifically, each is made of a pair of slew-rate-limited 2:1 multiplexers with internal feed-through compensation, as it is shown in
At step 1510, a first delay line is formed having a plurality of stages. Each of the plurality of stages includes a respective delay buffer and having one signal input and one signal output.
At step 1520, a second delay line is formed having a plurality of stages equal in number to the plurality of stages of the first delay line. Each of the plurality of stages of the second delay line includes a respective selecting element and has two signal inputs, one select input for selecting one of the two signal inputs, and one signal output. The first delay line and the second delay line are configured in parallel with respect to each other, are interconnected, and have a same signal propagation direction. The delay steps provided by each of the plurality of stages of the second delay line is equal to a difference between a delay through one of the plurality of stages of the first delay line and a delay through one of the plurality of stages of the second delay line.
At step 1610, a plurality of single-bit interpolator stages is formed. Each of the stages has a 2:1 multiplexer and a 1:1 interpolator. The 2:1 multiplexer and the 1:1 interpolator each receive two input signals having two different phases. The 2:1 multiplexer is configured to output one of the two input signals based on a select input. The 1:1 interpolator is configured to output an interpolated signal having a phase at a mid-point between the two different phases.
At step 1620, a phase converter is formed connected to a last stage of the plurality of single-bit interpolator stages. The phase converter is configured to convert the interpolated signal output from the 1:1 interpolator of the last stage and the one of the two input signals output from the 2:1 multiplexer of the last stage into a single final output signal of a given phase.
Having described preferred embodiments of a system and method (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.
This invention was made with Government support under Contract No.: H98230-07-C-0409 awarded by the National Security Agency. The Government has certain rights in this invention.
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