Claims
- 1. A CMOS programmable digital intermediate frequency receiver, comprising:a programmable memory receiving and storing a first value representative of a programmable parameter k and a second value representative of programmable parameter N; a clock generator coupled to the programmable memory, the clock generator generating a first clock signal having a first frequency, fl, a second clock signal having a second frequency approximately equal to fl/k, and a third clock signal having a third frequency approximately equal to fl/N; a sigma delta converter sampling an analog input signal having an intermediate frequency using the first clock signal to generate a first set of digital signals; a digital downconverter mixing down the first set of digital signals using the second clock signal to generate a second set of digital signals; and a decimation filter network filtering the second set of digital signals using the third clock signal to generate a third set of digital signals.
- 2. A monolithic CMOS programmable digital intermediate frequency transceiver, comprising:a programmable memory receiving and storing a first value, a second value, a third value, a fourth value and a fifth value, the first value being representative of a programmable parameter k, the second value representative of programmable parameter N, the third value being representative of a programmable parameter G, the fourth value being representative of a programmable parameter B, the fifth value being representative of a programmable parameter L; a clock generator coupled to the programmable memory, the clock generator generating first, second, third, fourth, fifth and sixth clock signals, the first clock signal having a first frequency, fl, the second clock signal having a second frequency approximately equal to fl/k, the third clock signal having a third frequency approximately equal to fl/N, the fourth clock signal having a fourth frequency approximately equal to fl/B, the fifth clock signal having a fifth frequency approximately equal to fl/GB, and the sixth clock signal having a sixth frequency approximately equal to fl/L; a receiver receiving an analog input signal having a first intermediate frequency, the receiver comprising: a sigma delta converter sampling the analog input signal using the first clock signal to generate a first set of digital signals; a digital downconverter mixing down the first set of digital signals using the second clock signal to generate a second set of digital signals; a decimation filter network filtering the second set of digital signals using the third clock signal to generate a third set of digital signals; a transmitter transmitting an analog output signal having a second intermediate frequency, the transmitter comprising: a digital interpolator network interpolating a fourth set of digital signals using the fourth and fifth clock signals to generate a fifth set of digital signals; a digital quadrature modulator mixing up the fifth set of digital signals using the sixth clock signal to generate a sixth set of digital signals; and a digital-to-analog converter converting the sixth set of digital signals into the analog output signal.
- 3. A method of receiving an analog input signal having an intermediate frequency using a CMOS programmable digital intermediate frequency receiver, the method comprising:receiving and storing a first value representative of a programmable parameter k and a second value representative of programmable parameter N; generating a first clock signal having a first frequency, fl, a second clock signal having a second frequency approximately equal to fl/k, and a third clock signal having a third frequency approximately equal to fl/N; sampling the analog input signal having an intermediate frequency using a sigma delta converter and the first clock signal to generate a first set of digital signals; mixing down the first set of digital signals using the second clock signal to generate a second set of digital signals; and filtering the second set of digital signals using the third clock signal to generate a third set of digital signals.
- 4. A method of receiving and transmitting analog IF signals using a monolithic CMOS programmable digital intermediate frequency transceiver, the method comprising:receiving and storing a first value, a second value, a third value, a fourth value and a fifth value, the first value being representative of a programmable parameter k, the second value representative of programmable parameter N, the third value being representative of a programmable parameter G, the fourth value being representative of a programmable parameter B, the fifth value being representative of a programmable parameter L; generating first, second, third, fourth, fifth and sixth clock signals, the first clock signal having a first frequency, fl, the second clock signal having a second frequency approximately equal to fl/k, the third clock signal having a third frequency approximately equal to fl/N, the fourth clock signal having a fourth frequency approximately equal to fl/B, the fifth clock signal having a fifth frequency approximately equal to fl/GB, and the sixth clock signal having a sixth frequency approximately equal to fl/L; sampling an analog input signal having a first IF frequency using a sigma delta converter and the first clock signal to generate a first set of digital signals; mixing down the first set of digital signals using the second clock signal to generate a second set of digital signals; filtering the second set of digital signals using the third clock signal to generate a third set of digital signals; interpolating a fourth set of digital signals using the fourth and fifth clock signals to generate a fifth set of digital signals; mixing up the fifth set of digital signals using the sixth clock signal to generate a sixth set of digital signals; and converting the sixth set of digital signals into an analog output signal having a second IF frequency.
- 5. A monolithic CMOS programmable digital intermediate frequency transmitter, comprising:a programmable memory receiving and storing a first value, a second value, and a third value, the first value being representative of a programmable parameter G, the second value being representative of a programmable parameter B, the third value being representative of a programmable parameter L; a clock generator coupled to the programmable memory, the clock generator generating first, second, and third clock signals, the first clock signal having a first frequency approximately equal to fl/B, the second clock signal having a second frequency approximately equal to fl/GB, and the third clock signal having a third frequency approximately equal to fl/L; a digital interpolator network interpolating a first set of digital signals using the first and second clock signals to generate a second set of digital signals; a digital quadrature modulator mixing up the second set of digital signals using the third clock signal to generate a third set of digital signals; and a digital-to-analog converter converting the third set of digital signals into an analog output signal.
CROSS REFERENCE TO RELATED APPLICATION
This application claims priority from the Provisional Application entitled “Programmable Digital Intermediate Frequency Transceiver”, U.S. Serial No. 60/133,136, filed May 7, 1999.
US Referenced Citations (12)
Foreign Referenced Citations (2)
Number |
Date |
Country |
WO9325968 |
Dec 1993 |
WO |
WO9823071 |
May 1998 |
WO |
Provisional Applications (1)
|
Number |
Date |
Country |
|
60/133136 |
May 1999 |
US |