Claims
- 1. In combination, a computer system having a data bus and an address bus including a central processing unit (CPU), a system control processor (SCP), one or more peripheral devices and one or more memory devices for storing predetermined instructions which result in various operations including testing of said one or more peripheral devices on power up; the improvement comprising:
- a first programmable hardware downcounter adapted to provide first predetermined timing signals after a predetermined number of clock pulses of a predetermined frequency are counted;
- a second programmable hardware down counter adapted to count said first predetermined timing signals to provide a second predetermined timing signal at a predetermined multiple of said first predetermined timing signal;
- one or more predetermined programmable registers for storing said predetermined number of clock pulses at said predetermined frequency to be counted for providing said first predetermined timing signals; and
- one or more predetermined programmable registers for storing said predetermined multiple for providing said second predetermined timing signals.
- 2. The combination of claim 1, further including means for enabling said predetermined multiple at which said second timing signal is provided to be set by software.
- 3. The combination of claim 2, wherein said second downcounter is connected to the data bus to enable said predetermined multiple to be set by the data bus.
- 4. The combination of claim 1 wherein said second downcounter is comprised of one or more registers.
- 5. In a computer system having a system control processor (SCP), a programmable timer adapted to count clock pulses of various frequencies and to provide timing signals at one or more predetermined timing intervals, said timer comprising:
- a first programmable hardware downcounter adapted to provide first predetermined timing signals after a predetermined number of clock pulses of the SCP are counted;
- a second programmable hardware down counter adapted to count said first predetermined timing signals to provide a second predetermined timing signal at a predetermined multiple of said first predetermined timing signal;
- one or more predetermined programmable registers for storing said predetermined number of clock pulses at said predetermined frequency to be counted for providing said first predetermined timing signals; and
- one or more predetermined programmable registers for storing said predetermined multiple for providing said second predetermined timing signals.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a division of U.S. patent application Ser. No. 08/218,413, filed Mar. 25, 1994, now abandoned, entitled PROGRAMMABLE HARDWARE COUNTER. This application is also related to the following applications all filed Mar. 25, 1994: NON-VOLATILE SECTOR PROTECTION FOR AN ELECTRICALLY ERASABLE READ ONLY MEMORY, Ser. No. 08/217,800, now abandoned in favor of continuation U.S. patent application Ser. No. 08/554,667, filed on Nov. 8, 1995, entitled PROTECTED ADDRESS RANGE IN AN ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY; SHARED CODE STORAGE FOR MULTIPLE CPUs, Ser. No. 08/217,958, now abandoned in favor of continuation U.S. patent application Ser. No. 08/480,047, filed on Jun. 6, 1995; METHOD TO PREVENT DATA LOSS IN AN ELECTRICALLY ERASABLE READ ONLY MEMORY, Ser. No. 08/218,412, now abandoned in favor of continuation U.S. patent application Ser. No. 08/478,363, filed on Jun. 7, 1995; PROGRAMMABLY RELOCATABLE CODE BLOCK, Ser. No. 08/217,646, now abandoned in favor of continuation U.S. patent application Ser. No. 08/549,307, filed on Oct. 27, 1995, entitled APPARATUS TO ALLOW A CPU TO CONTROL A RELOCATION OF CODE BLOCKS FOR OTHER CPUs; METHOD TO STORE PRIVILEGED DATA WITHIN THE PRIMARY CPU MEMORY SPACE, Ser. No. 08/218,273, now abandoned in favor of continuation U.S. patent application Ser. No. 08/572,190, filed on Dec. 13, 1995; METHOD FOR WARM BOOT FROM RESET, Ser. No. 08/218,968, now abandoned in favor of continuation U.S. patent application Ser. No. 08/607,445, filed Feb. 27, 1996; WRITE ONCE READ ONLY REGISTERS, Ser. No. 08/220,961, now abandoned in favor of continuation U.S. patent application Ser. No. 08/575,004, filed Dec. 19, 1995, entitled WRITE INHIBITED REGISTERS, divisional U.S. patent application Ser. No. 08/480,613, filed Jun. 7, 1995, now abandoned in favor of continuation U.S. patent application Ser. No. 08/710,639, filed Sep. 18, 1996 and divisional U.S. patent application Ser. No. 08/484,452, filed Jun. 7, 1995, now abandoned in favor of continuation U.S. patent application Ser. No. 08/680,099, filed Jul. 12, 1996; ALTERNATE I/O PORT ACCESS TO STANDARD REGISTER SET, Ser. No. 08/217,795, now abandoned in favor of continuation U.S. patent application Ser. No. 08/579,037, filed on Dec. 19, 1995.
US Referenced Citations (8)
Divisions (1)
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Number |
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218413 |
Mar 1994 |
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