Claims
- 1. A variable delay circuit for providing an output signal that is a delayed version of an input signal, comprising
- a first, slow delay subcircuit and a second, fast delay subcircuit coupled to receive an input signal to be delayed,
- a control circuit means for providing a constant current and for selectively proportioning said constant current between said first and second delay subcircuits, each subcircuit in response thereto providing corresponding first and second intermediate output signals representative of the input signal but delayed by a predetermined amount, and
- means for summing the intermediate output signals from the first and second delay subcircuits to provide a final output signal that corresponds to the input signal but that is delayed by an amount based on the proportion of said constant current supplied to each delay subcircuit by the control circuit,
- wherein each of said delay subcircuits comprises a pair of similar transistors each having a base, a collector, and an emitter, the bases receiving the input signal, the emitters being coupled together to receive a proportion of the constant current from the control circuit, and the current flowing in the collectors forming the intermediate output signal for the respective delay subcircuit, and wherein the emitters of the first delay subcircuit transistors are fabricated to have emitter areas larger than those of the second delay subcircuit transistors.
- 2. The circuit of claim 1, wherein said means for summing comprises a pair of load resistors coupled to the collectors of said first and second delay subcircuit transistors, which resistors receive the first and second intermediate output signal currents.
Parent Case Info
This is a continuation of application Ser. No. 06/887,582 filed July 18, 1986 and now abandoned.
US Referenced Citations (5)
Continuations (1)
|
Number |
Date |
Country |
Parent |
887582 |
Jul 1986 |
|