Computing systems may be configurable to provide for communication between a host device and a desired number of end devices. Such configuration typically occurs at the device level.
The present disclosure is best understood from the following detailed description when read with the accompanying Figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Illustrative examples of the subject matter claimed below will now be disclosed. In the interest of clarity, not all features of an actual implementation are described in this specification. It will be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions may be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort, even if complex and time-consuming, would be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
Many computing systems include a host device that communicates with different types of end devices using different respective communications protocols. As used herein, the term “host device” refers without limitation to a computing device including a processing unit. Examples of a host device may be a central processing unit, a server, a blade server, or any other device or equipment including a controller, a processing resource, or the like. The term “end device” refers without limitation to any device adapted to communicate with a host device including a processing unit. Examples of end devices include, without limitation, memory modules, hard drive or solid-state drives, network connection devices (e.g., WiFi or Ethernet cards), graphics processors, other computing devices, etc.
In many computing systems, the host device is supported by a printed circuit board. The end devices are connected to the host devices via traces on the printed circuit board. As the traces are fixed on the printed circuit board, such connections are limited in terms of flexibility.
In some cases, the host device and the end devices are connected using cables to allow high-speed data communication. The cables connect input/output (I/O) ports associated with the host device to different end devices. As used herein, the terminology “input/output (I/O) port” refers to a socket including terminals into which one end of a cable is inserted. The I/O port, in turn, is connected to the host device via an suitable connection, such as an electrical contact or bus. The cable includes an I/O port connector at one end to connect the cable to the I/O port and an end device interface connector at the other end to connect the cable to an end device interface. As used herein, the terminology “end device interface” refers to hardware, such as an I/O slot, a backplane, or an I/O port connector into which the cable is inserted. The end device interface, in turn, is connected to the end device via any suitable connection, such as an electrical contact or bus.
Many computing systems use different I/O ports that are respectively dedicated to the different end device interfaces associated with the different types of end devices to allow the host device to communicate with the different types of end devices. The computing systems switch between the different I/O ports to allow the host device to communicate with the different types of end devices. Using dedicated I/O ports and a switch to switch between the different I/O ports requires space on the motherboard and adds to the cost of the computing system.
To mitigate at least some of these issues, according to one or more examples disclosed herein, a host device is allowed to communicate with different types of end devices associated with different protocols using a single programmable I/O port. Based on a type of an end device that is connected to the host device, the I/O port is directed to present signals that correspond to a protocol associated with the end device. Rather than switching between I/O ports, the I/O port is programmed as appropriate to allow the host device to communicate with the end device using the protocol that is associated with the end device.
According to some examples, a system to manage communication between a host device and an end device is provided. The system includes a programmable input/output (“I/O”) port associated with the host device. The host device is connectable to a plurality of different types of end devices through a cable and the programmable I/O port. The plurality of different types of end devices are respectively associated with different types of protocols. The system further includes a port manager to detect a signal from an end device interface associated with the end device and determine, based on the detected signal, a type of the end device. The port manager is further to direct the programmable I/O port to present signals that correspond to a protocol associated with the determined type of the end device to allow the host device to communicate with the end device.
According to other examples, a method to manage communication between a host device and an end device is provided. The host device is connectable to a plurality of different types of end devices through a cable and a programmable I/O port. The plurality of different types of end devices are respectively associated with different types of protocols. A signal is detected from an end device interface associated with the end device. A type of the end device is determined based on the detected signal. The programmable I/O port is directed to present signals that correspond to a protocol associated with the determined type of the end device to allow the host device to communicate with the end device.
According to other examples, a non-transitory computer readable storage medium includes computer executable instructions stored thereon that, when executed by a processor, cause the processor to manage communication between a host device and an end device. The host device is connectable to a plurality of different types of end devices through a cable and a programmable I/O port. The plurality of different types of end devices are respectively associated with different types of protocols. When executed, the instructions cause the processor to detect a signal from an end device interface associated with the end device. The instructions further cause the processor to determine, based on the detected signal, a type of the end device, and direct the programmable I/O port to present signals that correspond to a protocol associated with the determined type of the end device to allow the host device to communicate with the end device.
The assembly 100 also includes a plurality of different types of end device interfaces 130, 140, and 150 supported by the motherboards. The end device interfaces are respectively associated with a plurality of different types of end devices 135, 145, and 155 that may be supported by or connected to the motherboard. In the example shown in
The host device 110 is connectable to the plurality of different types of end devices 135, 145, 155 via cables (not shown), the programmable I/O ports 120, and the end device interfaces 130, 140, and 150, respectively. This is described in further detail below with reference to
The assembly 100 also includes a system management portion 115 of a motherboard, referred to as a “management PCB”. The system management portion 115 may support management devices, such as a programmable logic device and a port manager (not shown) for managing communication between the host devices 110 and the end devices 135, 145, and 155. A programmable logic device and a port manager are described in further detail below with reference to
Referring now
In
In the example shown in
According to some examples, the signals presented by the programmable I/O port according to this pinout may be considered default signals that are presented if no signal is detected from an end device interface other than a PCIe slot. However, in the event that a signal is detected from another type of end device interface other than a PCIe slot, terminals of the programmable I/O port, such as the programmable I/O port 120 shown in
Referring to
The system 300 also includes a port manager 340 to detect a signal from the end device interface 320 via an inter-integrated circuit (“I2C” or “I2C” cable). The port manager 340 may determine, based on the detected signal, a type of the end device.
In some examples, the port manager 340 may have motherboard specification data stored in a memory that specifies what types of end device interfaces are installed on the motherboard and where those end device interfaces are installed. When a signal is detected from an end device interface, the port manager 340 uses the stored specification data to determine the type of end device that is connected. For example, when a signal is detected from a PCIe slot, the port manager 340 determines, based on the specification data, that the detected signal is from a PCIe slot and that the type of the end device is a PCIe device. The port manager 340 directs the programmable I/O port 305 port to present signals that correspond to a protocol associated with the determined type of the end device to allow the host device to communicate with the end device via the cable 330 and the end device interface 320.
The programmable I/O port 305 includes programmable terminals to present signals to the cable 330 via the I/O port connector 310. The programmable terminals are programmed by a programmable logic device 350 included in the system 300. The port manager 340 is to instruct the programmable logic device 350 to program the programmable terminals of the programmable I/O port 305 to present the signals to the I/O port connector 310 that correspond to the protocol associated with the determined type of the end device.
According to one or more examples, the port manager 340 instructs the programmable logic device 350 to program the programmable terminals (not otherwise shown) of the programmable I/O port 305 by providing an instruction that corresponds to a case statement in the programmable logic device 350. The case statements may define how the programmable logic device 350 programs the programmable I/O port 305. For example, if the port manager 340 provides an instruction “00”, the programmable logic device 350 programs the programmable terminals of the programmable I/O port 305 to present a first set of signals. On the other hand, if the port manager 340 provides an instruction “01”, the programmable logic device 350 programs the programmable terminals of the programmable I/O port 305 to present a different set of signals. The programmable logic device 350 “programs” the programmable terminals of the programmable I/O port by causing the terminals to output the signals that correspond to the protocol associated with the determined type of the end device.
In the example system 300 shown in
In the example system 300 shown in
The system 400A also includes a port manager 440 connected to the end device interface 420 via an I2C cable. The port manager 440 is to detect a signal from the end device interface 420 and determine, based on the detected signal, a type of the end device. The port manager 440 directs the programmable I/O port 405 to present signals that correspond to a protocol associated with the determined type of the end device to allow the host device to communicate with the end device via the cable 430 and the end device interface 420.
The programmable I/O port 405 includes programmable terminals (not otherwise shown) to present signals to the cable 430 via the I/O port connector 410. The programmable terminals are programmed by a programmable logic device 450 included in the system 400A. The port manager 440 is to instruct the programmable logic device 450 to program the programmable terminals of the programmable I/O port 405 to present the signals to the I/O port connector 410 that correspond to the protocol associated with the determined type of the end device.
In the example system 400A shown in
In the example system 400A shown in
The system 400B shown in
Like the system 400A shown in
The programmable I/O ports 405A and 405B include programmable terminals to present signals to the respective cables 430A and 430B via the respective I/O port connectors 410A and 410B. The programmable terminals are programmed by a programmable logic device 450 included in the system 400B. The port manager 440 is to instruct the programmable logic device 450 to program the programmable terminals of the programmable I/O ports 405A and 405B to present the signals to the respective I/O port connectors 410A and 410B that correspond to the protocol associated with the determined type of the end device with which the end device interfaces 420A and 420B are associated.
In the example system 400B shown in
The system 500 also includes a port manager 540 connected to the end device interfaces 520A and 520B via I2C cables. The port manager 540 is to detect signals from the end device interfaces 520A and 520B and determine, based on the detected signals, a type of the end device. Based on the determined type of the end device, the port manager 540 is to direct the programmable I/O port 505 to present signals that correspond to a protocol associated with the determined type of the end device to allow the host device to communicate with the end device via the cables 530A and 530B and the end device interface 520A and 520B.
The programmable I/O port 505 includes programmable terminals to present signals to the respective cables 530A and 530B via the I/O port connector 510. The programmable terminals are programmed by a programmable logic device 550 included in the system 500. The port manager 540 is to instruct the programmable logic device 550 to program the programmable terminals of the programmable I/O port 505 to present the signals to the I/O port connector 510 that correspond to the protocol associated with the determined type of the end device with which the end device interfaces 520A and 520B are associated.
In the example system 500 shown in
Referring first to
The system 600A also includes a port manager 650 connected to the programmable I/O port 615B and the programmable I/O port 615A by an I2C cable. Similar to the port managers 340, 440, and 540 illustrated respectively in
Based on determining that the end device is a CPU 605B, the port manager 650 directs the programmable I/O port 615A to present signals that correspond to the CPU native protocol. The programmable I/O port 615A may use some terminals (not otherwise shown) to present signals in the CPU native protocol. The signals presented on these terminals would be the same for communicating with any type of respective end device. Those terminals that are used to present signals to other types of end devices that may be programmed depending on the type of the end device are not used. Accordingly, there is no programming of the terminals of the programmable I/O port 615A by a programmable logic control device in this example.
In the example system 600A shown in
Referring to
The system 600B also includes a port manager 650 connected to the programmable I/O port 615B and the programmable I/O port 615A by an I2C cable. The port manager 650 is to detect that the end device is a CPU 605B, e.g., by detecting a signal from the programmable I/O port 615B. Based on determining that the end device is a CPU, the port manager 650 directs the programmable I/O port 615A to present signals that correspond to the CPU native protocol. As in the example described above with reference to
In the example system 600C, the host device and one respective end device, e.g., the CPUs 605A and 605B, the programmable I/O port 615A, and one respective end device interface, e.g., the programmable I/O port 615B, are supported on the same printed circuit board 620A. The other respective end devices, e.g., the CPUs 605C and 605D, and the other respective end device interfaces, e.g., the programmable I/O ports 615C and 615D, are supported on another printed circuit board 620B.
The system 600C also includes a cable 630A to connect the end device interface, e.g., the programmable I/O port 615B, to the programmable I/O port 615A. The cable 630 is connected at one end to the programmable I/O port 615A via an I/O port connector 610A. The cable 630A is connected at the other end to the end device interface, e.g., the programmable I/O port 6156, via another I/O port connector 6106.
The system 600C also includes another cable 630B to connect the end device interfaces, e.g., the programmable I/O ports 615C and 615D. The cable 630B is connected at one end to the end device interface, e.g., the programmable I/O port 615C via an I/O port connector 610C. The cable 630B is connected at the other end to the end device interface, e.g., the programmable I/O port 615D, via another I/O port connector 610D. As shown in
The system 600C also includes a port manager 650 connected to the end device interfaces, e.g., the programmable I/O ports 615B, 615C, and 615D, and the programmable I/O port 615A by I2C cables. The port manager 650 is to detect signals from the end device interfaces, e.g., the programmable I/O ports 615B, 615C and 615D, and determine that the end devices are CPUs 605B, 605C and 605D. Based on determining that the end devices are CPUs, the port manager 650 directs the programmable I/O port 615A to present signals that correspond to the CPU native protocol. As in the examples described above with reference to
The method 700 includes detecting a signal from an end device interface associated with an end device at 710. The end device is connected to a host device via a cable and a programmable I/O associated with the host device. The host device is connectable to a plurality of different types of end devices, and the plurality of different types of end devices are respectively associated with different types of protocols.
Based on the detected signal, a type of the end device is determined at 720. At 730, the programmable I/O port is directed to present signals that correspond to a protocol associated with the end device based on the determined type of the end device. This may include instructing programmable logic device to program the programmable I/O port to present the signals.
Referring to
The processor 810 communicates with a memory 830 via, e.g., an address/data bus 815. The memory 830 is representative of a memory device containing the software and data used to implement the functionality of the computing device 800. The memory 830 can include, but is not limited to, a non-transitory computer readable storage medium 835, such as an electrically erasable programmable read-only memory (EEPROM) implemented as firmware. Still other alternatives may be used. The memory may be volatile or non-volatile, random-access or read-only, or even cache. As shown in
The computer executable instructions 840 can be stored in the memory 830 and can be executed by the processor 810. The computer executable instructions 840 include various programs that implement the various features of the computing device 800. For example, the computer executable instructions 840 may include instructions to implement the functions of the port manager (including detecting a signal from an end device interface associated with an end device connected to a host device via a cable and a programmable I/O port associated with the host device, determining, based on the detected signal, a type of the end device, directing the programmable I/O port to present signals that correspond to a protocol associated with the determined type of the end device based on the determined type of the end device to allow the host device to communicate with the end device, etc.).
The memory 830 may also store static and dynamic data used by the instructions 840. Also, other software programs may reside in the memory 830. The data that may be stored in the memory may include, e.g., motherboard specifications used to determine what types of end devices are connected based on signals detected from end device interfaces, instructions to send to a programmable logic device for different types of devices, etc.
It should be understood that
The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the disclosure. However, it will be apparent to one skilled in the art that the specific details are not required in order to practice the systems and methods described herein. The foregoing descriptions of specific examples are presented for purposes of illustration and description. They are not intended to be exhaustive of or to limit this disclosure to the precise forms described. Many modifications and variations are possible in view of the above teachings. The examples are shown and described in order to best explain the principles of this disclosure and practical applications, to thereby enable others skilled in the art to best utilize this disclosure and various examples with various modifications as are suited to the particular use contemplated. It is intended that the scope of this disclosure be defined by the claims and their equivalents below.