Claims
- 1. A programmable logic circuit comprising:
- digital converting means for converting input data into digital form and for outputting signals;
- latching means, connected to said digital converting means, for receiving said signals from said digital converting means and a latch timing and for outputting delayed signals based on said latch timing;
- memory means, connected to said digital converting means and said latching means, for prestoring operative data based on fuzzy reasoning, said memory means for outputting said prestored operative data based on said signals from said digital converting means and said delayed signals from said latching means; and
- feedback means, connected to said memory means, for feeding back said prestored operative data from an output of said memory means to an input of said memory means, said feedback means including timing means for delaying feedback of said prestored operative data for predetermined time periods, wherein said memory means outputs said prestored operative data based on a trend of said prestored operative data and delayed prestored operative data.
- 2. A programmable logic circuit according to claim 1 wherein said digital converting means includes analog to digital converters, a comparison circuit and a second latch circuit.
Priority Claims (1)
Number |
Date |
Country |
Kind |
63-295793 |
Nov 1988 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 409,903 filed Sep. 20, 1989, now abandoned.
US Referenced Citations (6)
Non-Patent Literature Citations (1)
Entry |
H. R. van Nauta Lemke and Wang De-Zhao, "Fuzzy PID Supervisor", 1985 from 24th IEEE Conference on Decision and Control, vol. 1, pp. 602-608. |
Continuations (1)
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Number |
Date |
Country |
Parent |
409903 |
Sep 1989 |
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