Claims
- 1. An integrated circuit logic device comprising:
a plurality of super-regions disposed on the logic device in a two-dimensional array of intersecting rows and columns of such super-regions, each of said super-regions including a plurality of regions of logic and a region of memory, each of said logic regions having a plurality of inputs and a plurality of outputs, and said memory region also having a plurality of inputs and a plurality of outputs; and interconnection circuitry for connecting said outputs of said logic regions and said memory regions to said inputs of said logic regions and said memory regions, wherein for each of the super-regions, the interconnection circuitry comprises:
a plurality of first interconnection conductors uniquely associated with the super-region, each of the first interconnection conductors that is associated with a super-region extending substantially continuously adjacent to all of the logic and memory regions in that super-region and being connected only to the logic and memory regions in that super-region.
- 2. The device defined in claim 1 wherein each of the regions of logic includes a plurality of sub-regions of logic.
- 3. The device defined in claim 1 wherein each of the rows is divided in two halves, and wherein the device further comprises:
a plurality of second interconnection conductors associated with each half of each row and extending adjacent to all the super-regions in that half row.
- 4. The device defined in claim 1 wherein each of the columns is divided into two half columns, and wherein the device further comprises:
a plurality of third interconnection conductors associated with each half column and extending adjacent to all the super-regions in that half column.
Parent Case Info
[0001] This is a continuation of application Ser. No. 10/062,741, filed Feb. 1, 2002, which is a continuation of application Ser. No. 09/792,809, filed Feb. 23, 200, which is a continuation of application Ser. No. 09/266,235, filed Mar. 10, 1999 (issued as U.S. Pat. No. 6,215,326, Apr. 10, 2001), which claims the benefit of provisional patent application No. 60/109,417, filed Nov. 18, 1998, all of which are hereby incorporated by reference herein in their entireties.
Provisional Applications (1)
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Number |
Date |
Country |
|
60109417 |
Nov 1998 |
US |
Continuations (3)
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Number |
Date |
Country |
Parent |
10062741 |
Feb 2002 |
US |
Child |
10260712 |
Sep 2002 |
US |
Parent |
09792809 |
Feb 2001 |
US |
Child |
10062741 |
Feb 2002 |
US |
Parent |
09266235 |
Mar 1999 |
US |
Child |
09792809 |
Feb 2001 |
US |