Claims
- 1. A programmable logic device comprising:
a plurality of super-regions disposed on the device in a two-dimensional array of intersecting rows and columns of such super-regions, each of said super-regions including a plurality of regions of programmable logic and a region of memory, each of said logic regions including a plurality of subregions of programmable logic, each of the subregions having a plurality of inputs and an output and being programmable to perform any of several logic functions on its inputs to produce its output, and said memory region also having a plurality of inputs and a plurality of outputs and being responsive to its inputs to produce its outputs based at least in part on its inputs and data stored in the memory region; and programmable interconnection circuitry for selectively connecting said outputs to said inputs.
- 2. The device defined in claim 1 wherein, for each of the super-regions, the interconnection circuitry comprises:
a plurality of first interconnection conductors uniquely associated with that super-region, each of the first conductors that is associated with a super-region extending substantially continuously adjacent to all of the regions in that super-region.
- 3. The device defined in claim 2 wherein the interconnection circuitry further comprises:
a plurality of second interconnection conductors extending along each of said rows of super-regions; and a plurality of third interconnection conductors extending along each of said columns of super-regions.
- 4. The device defined in claim 1 wherein, for each of a multiplicity of subpluralities of said subregions in each of said super-regions, said interconnection circuitry further comprises:
a plurality of fourth interconnection conductors associated with that subplurality, each of the fourth conductors that is associated with a subplurality extending substantially continuously adjacent to all of the subregions in that subplurality.
- 5. The device defined in claim 4 wherein said interconnection circuitry further comprises:
first programmable logic connectors configured to selectively connect the inputs of each subregion to at least some of the fourth interconnection conductors that are associated with the subplurality that includes that subregion.
- 6. The device defined in claim 4 wherein said interconnection circuitry further comprises:
second programmable logic connectors configured to selectively connect at least some of the fourth interconnection conductors that are associated with each of said subpluralities of subregions to at least some of the first interconnection conductors that are associated with the regions that include those subregions.
- 7. The device defined in claim 4 wherein, for each of the subpluralities, said interconnection circuitry further comprises:
a plurality of fifth interconnection conductors associated with that subplurality, each of the fifth conductors that is associated with a subplurality extending substantially continuously adjacent to all of the subregions in that subplurality; and third programmable logic connectors configured to selectively connect the output of each of said subregions to at least one of the fifth conductors that is associated with the subplurality that includes that subregion.
- 8. The device defined in claim 7 wherein said interconnection circuitry further comprises:
fourth programmable logic connectors configured to selectively connect the inputs of each subregion to at least some of the fifth interconnection conductors that are associated with the subplurality that includes that subregion.
- 9. The device defined in claim 3 wherein, for each of the super-regions, the interconnection circuitry further comprises:
fifth programmable logic connectors configured to selectively connect at least some of the first interconnection conductors associated with that super-region to at least some of the second interconnection conductors that extend along the row that includes that super-region.
- 10. The device defined in claim 3 wherein, for each of the super-regions, the interconnection circuitry further comprises:
sixth programmable logic connectors configured to selectively connect at least some of the first interconnection conductors associated with that super-region to at least some of the third interconnection conductors that extend along the column that includes that super-region.
- 11. The device defined in claim 1 wherein each of the memory regions is programmably configurable to provide output signals in parallel on a plurality of different numbers of its outputs.
- 12. The device defined in claim 1 wherein each of the memory regions is programmably configurable to operate in a selected one of a random access memory mode and a product-term mode.
- 13. The device defined in claim 2 wherein, for each of the super-regions, the interconnection circuitry further comprises:
seventh programmable logic connectors configured to selectively connect at least some of the outputs of the memory region of that super-region to at least some of the first interconnection conductors associated with that super-region.
- 14. The device defined in claim 3 wherein, for each of the super-regions, the interconnection circuitry further comprises:
eighth programmable logic connectors configured to selectively connect at least some of the outputs of the memory region of that super-region to at least some of the second interconnection conductors that extend along the row that includes that super-region.
- 15. The device defined in claim 3 wherein, for each of the super-regions, the interconnection circuitry further comprises:
ninth programmable logic connectors configured to selectively connect at least some of the outputs of the memory region of that super-region to at least some of the second interconnection conductors that extend along the column that includes that super-region.
- 16. A digital processing system comprising:
processing circuitry; a memory coupled to said processing circuitry; and a programmable logic device as defined in claim 1 coupled to the processing circuitry and the memory.
- 17. A printed circuit board on which is mounted a programmable logic device as defined in claim 1.
- 18. The printed circuit board defined in claim 17 further comprising:
a memory mounted on the printed circuit board and coupled to the programmable logic device.
- 19. The printed circuit board defined in claim 17 further comprising:
processing circuitry mounted on the printed circuit board and coupled to the programmable logic device.
Parent Case Info
[0001] This is a continuation of application Ser. No. 09/266,235, filed Mar. 10, 1999, which claims the benefit of provisional patent application Ser. No. 60/109,417, filed Nov. 18, 1998, both of which prior applications are hereby incorporated by reference herein in their entireties.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60109417 |
Nov 1998 |
US |
Continuations (1)
|
Number |
Date |
Country |
Parent |
09266235 |
Mar 1999 |
US |
Child |
09792809 |
Feb 2001 |
US |