Claims
- 1. A programmable logic device operable to generate output signals skewed in time, the programmable logic device comprising:a plurality of I/O cells; first and second logic circuits, each logic circuit being operable to generate a logic output signal on a respective output line, each output line being coupled to at least one of the I/O cells; a first delay element coupled to the output line of the first logic circuit, the first delay element being programmably operable to delay the output signal of the first logic circuit relative to the output signal of the second logic circuit in response to at first delay control signal; a second delay element coupled to the output line of the second logic circuit, the second delay element being programmably operable to delay the output signal of the second logic circuit relative to the output signal of the first logic circuit in response to a second delay control signal; control circuitry generating the first and second delay control signals so as to prevent simultaneous switching of the logic output signals of the first and second logic circuits.
- 2. The programmable logic device of claim 1, wherein the control circuitry comprises a plurality of programmable memory cells operable to generate the first and second delay control signals.
- 3. The programmable logic device of claim 1, wherein each logic circuit comprises:a programmable AND array operable to generate a plurality of product term output signals on a corresponding plurality of product term output lines; and a product term summing OR gate having a plurality of input terminals and an output terminal, at least one of the input terminals being coupled to at least one of the product term output lines, the output terminal being coupled to the output line of the logic circuit.
- 4. The programmable logic device of claim 1, wherein the first programmable delay element comprises a capacitive load coupled to the output line of the first logic circuit.
- 5. A method for generating skewed logic output signals in a programmable logic device, comprising:generating at a first logic circuit in the programmable logic device a first logic signal on a first output line; generating at a second logic circuit in the programmable logic device a second logic signal on a second output line simultaneously with generating the first logic signal; delaying the first logic signal relative to the second logic signal at a programmable delay element, so as to prevent simultaneous switching of the first and second logic signals; and receiving the first and second logic signals at first and second output pins, respectively, for transmission outside the programmable logic device.
- 6. The method of claim 5, wherein delaying the first logic signal comprises coupling a capacitive load to the first output line in response to a delay control signal.
- 7. The method of claim 6, further comprising:generating the delay control signal at a programmable memory cell; and transmitting the delay control signal to the programmable delay element.
- 8. A method for generating a plurality of skewed logic output signals in a programmable logic device, comprising:generating at a plurality of first logic circuits in the programmable logic device a corresponding plurality of first logic signals on a corresponding plurality of first output lines; generating at a plurality of second logic circuits in the programmable logic device a corresponding plurality of second logic signals on a corresponding plurality of second output lines simultaneously with the first logic signals; delaying the first logic signals relative to the second logic signals at a plurality of programmable delay elements, so as to prevent simultaneous switching of the first and second logic signals; and receiving the plurality of first and second logic signals at a plurality of first and second output pins, respectively, for transmission outside the programmable logic device.
- 9. The method of claim 8, wherein delaying the first logic signals comprises coupling a capacitive load to the each of the first output lines in response to a plurality of delay control signals.
- 10. The method of claim 9, further comprising:generating the delay control signals at a plurality of programmable memory cells; and transmitting the delay control signals to the programmable delay elements.
CROSS REFERENCE TO RELATED APPLICATION
This application is a divisional of U.S. patent application Ser. No. 09/083,205, filed May 21, 1998, entitled “Programmable Logic Device”.
US Referenced Citations (22)