Patent Application
20120324164
This invention relates generally to memory management in computers. More particularly, this invention relates to programmed memory address segments.
Processors sold by MIPS Technologies®, Sunnyvale, Calif., use and handle addresses in a unique manner.
For the kernel mode, there is an unmapped cached region called “kseg0” 104. This region is 512 MB ranging from virtual address 0x8000 000 through 9FFF FFFF. These virtual addresses are translated into physical addresses by stripping off the top 3 most significant bits and mapping them contiguously into the lower 512 MB of physical memory. Addresses in this region are almost always accessed through the cache. The addresses are used for most programs and data in systems not using an MMU and are used by the Operating System (OS) kernel for systems that do use an MMU.
The unmapped and uncached region is called “kseg1” 106. This region is also 512 MB, with virtual addresses ranging from 0xA000 0000 through BFFF FFFF. These virtual addresses are mapped into physical addresses by stripping off the leading 3 bits, giving a duplicate mapping of the lower 512 MB of physical memory. In this space, access does not rely upon the cache.
The mapped region is called “kseg2” 108. This 1 GB region spans virtual addresses 0xC000 0000 through FFFF FFFF. This area is only accessible in kernel mode. This region is translated through the MMU.
Since the memory segments are fixed, a user is not able to optimize a machine for a particular application, such as processing large media files in the form of streaming media. For example, it might be desirable to have a larger unmapped memory segment to access such large files.
Therefore, it would be desirable to provide a mechanism to accommodate optimized processing modes. Such a mechanism should support the definition of memory segment attributes, such as access modes, cache features and memory map features.
A method of converting fixed memory address segments into programmable memory address segments includes storing defined memory address segments and defined memory address segment attributes. The processor is operated in accordance with the defined memory address segments and defined memory address segment attributes.
A computer includes a memory and a processor connected to the memory. The processor includes memory segment configuration registers to store defined memory address segments and defined memory address segment attributes such that the processor operates in accordance with the defined memory address segments and defined memory address segment attributes.
A processor includes memory segment configuration registers to store defined memory address segments and defined memory address segment attributes such that the processor operates in accordance with the defined memory address segments and defined memory address segment attributes.
A computer readable storage medium includes executable instructions to define a processor with a fixed memory address mapping. Memory segment configuration registers store defined memory address segments and defined memory address segment attributes such that the processor operates in accordance with the defined memory address segments and defined memory address segment attributes.
The invention is more fully appreciated in connection with the following detailed description taken in conjunction with the accompanying drawings, in which:
Like reference numerals refer to corresponding parts throughout the several views of the drawings.
This stands in contrast to the prior art. In the prior art, the accessibility mode (e.g., kernel only, kernel and supervisor, or kernel and supervisor and user) is fixed for each segment. (A chosen segment is defined by the most significant address bits.) The mapability (e.g., use of memory management unit and translation look-aside buffer) is fixed for each segment. Finally, the cache-ability (e.g., the use of a cache) is also fixed for each segment. In an embodiment of the invention, the accessibility mode per segment is programmed into memory segment configuration registers 211 by privileged software, normally at power-up. Similarly, the map-ability per segment is programmed, as is the cache-ability per segment. As in the legacy system, the chosen segment is defined by the most significant address bits.
The computer 200 also includes input/output devices 212, which are connected to the CPU 210 via a bus 214. The input/output devices 212 may include a keyboard, mouse, display, printer and the like. A network interface circuit 216 is also connected to the bus 214. The network interface circuit 216 allows the computer 200 to operate in a networked environment.
A memory 220 is also connected to the bus 214. In one embodiment, the memory 220 stores a hypervisor 212, which may be used to implement a guest machine 224. This allows for virtualization of hardware resources. Virtualization refers to the creation of a virtual, rather than an actual, version of something, such as a hardware platform, operating system, a storage device or a network resource. For example, a computer that is running Microsoft® Windows® may host a virtual machine that looks like a computer with an Apple® operating system. Therefore, Apple® compliant software can be executed on the virtual machine.
In hardware virtualization, the term host machine refers to the actual machine on which the virtualization takes place. The term guest machine refers to the virtual machine. The software or firmware that creates a virtual machine on the host machine is called a hypervisor. In the MIPS legacy virtual address map, KSEG0 and KSEG1 cannot be relocated, which hinders virtualization.
The memory segment configuration registers 211 facilitate virtualization operations. However, the memory segment configuration registers 211 need not be used in connection with virtualization operations. Rather, the memory segment configuration registers 211 may be used in any number of modalities. For example, the memory segment configuration registers 211 may be used in connection with a standard operating system 226. The memory 220 may also store privileged software 228, which is used to write values to the memory segment configuration registers 211, typically at power-up.
The memory segment configuration registers 211 may be implemented to set the following parameters:
Preferably, on reset, all segment configurations default to the fixed memory segment configuration of
The memory segment configuration registers may be used to implement a fully translated flat address space. Alternately, they may be used to alter the relative size of cached and uncached windows into the physical address space.
This segmentation control is more fully appreciated in connection with the following example, which includes annotations.
While various embodiments of the invention have been described above, it should be understood that they have been presented by way of example, and not limitation. It will be apparent to persons skilled in the relevant computer arts that various changes in form and detail can be made therein without departing from the scope of the invention. For example, in addition to using hardware (e.g., within or coupled to a Central Processing Unit (“CPU”), microprocessor, microcontroller, digital signal processor, processor core, System on chip (“SOC”), or any other device), implementations may also be embodied in software (e.g., computer readable code, program code, and/or instructions disposed in any form, such as source, object or machine language) disposed, for example, in a computer usable (e.g., readable) medium configured to store the software. Such software can enable, for example, the function, fabrication, modeling, simulation, description and/or testing of the apparatus and methods described herein. For example, this can be accomplished through the use of general programming languages (e.g., C, C++), hardware description languages (HDL) including Verilog HDL, VHDL, and so on, or other available programs. Such software can be disposed in any known computer usable medium such as semiconductor, magnetic disk, or optical disc (e.g., CD-ROM, DVD-ROM, etc.).
It is understood that the apparatus and method described herein may be included in a semiconductor intellectual property core, such as a microprocessor core (e.g., embodied in HDL) and transformed to hardware in the production of integrated circuits. Additionally, the apparatus and methods described herein may be embodied as a combination of hardware and software. Thus, the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
