Claims
- 1. A field programmable gate array (FPGA) comprising:a gate array; at least one programmable voltage supply driver coupled to the gate array and configured to supply a plurality of voltages; (5) a plurality of programmable input/output buffers coupled to the voltage supply driver and configurable to separate the voltage supplies; (page 2) at least one fuse address driver coupled to the plurality of programmable input/output buffers and configured to drive the plurality of programmable input/output buffers; and means to program the plurality of programmable input/output buffers to a desired configuration.
- 2. The FPGA of claim 1, each of the plurality of programmable input/output buffers further comprising:at least 2 programmable antifuse matrix cells configured to receive configuration information for the each of the plurality of programmable input/output buffers.
- 3. The FPGA of claim 1, each of the plurality of programmable input/output buffers further comprising:a set of programmable antifuse matrix cells configured to receive configuration information for the each of the plurality of programmable input/output buffers.
- 4. The FPGA of claim 3, where each set of programmable antifuse matrix cells further includes 16 programmable antifuse matrix cells.
- 5. The FPGA of claim 4, wherein the at least one fuse address driver further comprises a plurality of fuse address drivers and the at least one programmable voltage supply driver further comprises a plurality of programmable voltage supply drivers, wherein each set of programmable antifuse matrix cells is connected to eight of the plurality of fuse address drivers and two of the plurality of programmable voltage supply drivers.
- 6. The FPGA of claim 1, further comprising:a programable input/output driver circuit coupled to the plurality of programmable input/output buffers, wherein the plurality of programmable input/output buffers further comprise a plurality of programmable antifuse matrix cells.
- 7. The FPGA of claim 1, where said means to program further includes a plurality of programmable antifuse matrix cells.
- 8. The FPGA of claim 1, where said desired configuration includes a plurality of I/O standards.
Parent Case Info
This application is a continuation of 09/738,508 Dec. 18/2000 now U.S. Pat. No. 6,392,437 which is a division of 09/224/929 Dec. 31/1998 U.S. Pat. No. 6,242,943
US Referenced Citations (19)
Continuations (1)
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Number |
Date |
Country |
Parent |
09/738508 |
Dec 2000 |
US |
Child |
10/024661 |
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US |