Claims
- 1. A programmable antifuse matrix cell comprising:A two terminal antifuse An N-channel transistor A p-channel transistor One terminal of said antifuse connected to a first source/drain terminal of said N-channel transistor and to a first source/drain terminal of said P-channel transistor and to an output node Second terminal of said antifuse connected to ground The gates of two said transistors are connected The second source/drain terminal of said N-channel transistor is connected to a first voltage Second source/drain terminal of said P-channel transistor is connected to a second voltage.
- 2. The programmable antifuse matrix cell of claim 1 where the gate of the N-channel transistor is connected to an input node and the gate of the P-channel transistor is connected to ground.
- 3. The programmable antifuse matrix cell of claim 1 where the output node further drives an inverter.
CROSS REFERENCE TO RELATED APPLICATIONS
This is a divisional of application Ser. No. 10/024,661, filed on Dec. 13, 2001, which is a continuation of application Ser. No. 09/738,508, filed Dec. 18, 2000 now U.S. Pat. No. 6,392,437, which is a divisional of application Ser. No. 09/224,929, filed Dec. 31, 1998, now U.S. Pat. No. 6,242,943.
US Referenced Citations (21)
Continuations (1)
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Number |
Date |
Country |
Parent |
09/738508 |
Dec 2000 |
US |
Child |
10/024661 |
|
US |