Programming on-chip non-volatile memory in a secure processor using a sequence number

Abstract

A method may be executed by a secure processor having secure cryptography hardware implemented thereon. The method may be executed in a security kernel of a secure on-chip non-volatile (NV) memory coupled to the secure processor. The method may include: storing a rewritable state and a device private key based at least in part on a programmed secret seed and the rewritable state, the device private key being part of a cryptographic key pair comprising a public key associated with the device private key, and the rewritable state being a state of a secure application encrypted with the public key; providing one or more instructions to gather the device private key and from the private key datastore; and using the device private key to generate a device certificate, the device certificate providing the device with access to the secure application.

Description

BACKGROUND

A secure processor typically includes an ID and/or stored secret key. In order to enhance the level of security, the quantities could be programmed in chip-internal non-volatile memory to build a secure processor. The programming of the ID and secret key happen during the secure manufacturing process of the chip. Each ID is unique, and so is the private key. These quantities are used in applications on the device, to implement digital rights management and other security related applications. Typically, the chip includes mechanisms to generate cryptographically strong random numbers to use as nonces in network protocols, secret keys etc.

In a typical infrastructure used for implementing digital rights management, a server is used to supply digitally signed tickets to enable rights for the device. Such tickets use the device identities and/or secret key mechanisms to bind the tickets to the devices. In order to ensure the uniqueness of each device ID/key the server typically uses a secure database to store the IDs, (and/or signed certificates) corresponding to each chip that is manufactured. These certificates contain public keys corresponding to each secret key (private key of a (private, public) key pair) programmed in the chip. In order to populate the database with certificates, the infrastructure associated with the database should be securely coupled with the manufacturing process to maintain a one-to-one correspondence between manufactured chips and certificates in the database.

The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.

SUMMARY

The following embodiments and aspects thereof are described and illustrated in conjunction with systems, tools, and methods that are meant to be exemplary and illustrative, not limiting in scope. In various embodiments, one or more of the above-described problems have been reduced or eliminated, while other embodiments are directed to other improvements.

A device may comprise: a secure processor having secure cryptography hardware implemented thereon; a secure on-chip non-volatile (NV) memory coupled to the secure processor, the secure on-chip NV memory having a security kernel receiving instructions from the secure processor, the security kernel containing: a private key datastore configured to store a rewritable state and a device private key based at least in part on a programmed secret seed and the rewritable state, the device private key being part of a cryptographic key pair comprising a public key associated with the device private key, and the rewritable state being a state of a secure application encrypted with the public key; an authenticated security Application Programming Interface (API) coupled to the private key datastore, the authenticated security API configured to provide one or more instructions to gather the device private key and from the private key datastore; and a certificate construction engine coupled to the authenticated security API, the certificate construction engine configured to use the device private key to generate a device certificate, the device certificate providing the device with access to the secure application.

In some implementations, the programmed secret seed comprises a pseudorandom number. The programmed secret seed may be stored on on-chip read-only memory (ROM) coupled to the secure processor. The security kernel may use the programmed secret seed and the rewritable state to generate the device private key.

In some implementations, the cryptographic key pair comprises an elliptical cryptographic key pair. The secure kernel may identify the public key in response to a request to execute the secure application.

The device private key may comprise a variable key. In some implementations, the certificate construction engine uses the device private key to generate a device certificate in response to a request to validate an electronic ticket provided by the secure application.

The secure processor may load the security kernel into the secure on-chip memory in response to a start-up of the device. The device may comprise a game console or a media player.

A method may be executed by a secure processor having secure cryptography hardware implemented thereon. The method may be executed in a security kernel of a secure on-chip non-volatile (NV) memory coupled to the secure processor. The method may include: storing a rewritable state and a device private key based at least in part on a programmed secret seed and the rewritable state, the device private key being part of a cryptographic key pair comprising a public key associated with the device private key, and the rewritable state being a state of a secure application encrypted with the public key; providing one or more instructions to gather the device private key and from the private key datastore; and using the device private key to generate a device certificate, the device certificate providing the device with access to the secure application.

An improved secure programming technique involves reducing the size of bits programmed in on-chip secret non-volatile memory, at the same time enabling the typical secure applications supported by secure devices. Another improved secure programming technique involves simplifying the process of manufacture of the system. In an embodiment, programming the secrets is isolated to on-chip programming, and, specifically, is isolated from the processes of system integration and infrastructure setup.

A technique for secure programming involves de-coupling chip manufacture from the later process of connecting to ticket servers to obtain tickets. A method according to the technique may involve sending a (manufacturing) server signed certificate from the device prior to any communication to receive tickets. The method may further include populating a database to facilitate performing ticket services later, for example just when the ticket services are needed.

A device according to the technique may include chip-internal non-volatile memory to store the certificate along with the private key, in the manufacturing process. The private key may or may not be an elliptic curve based private key. An advantage of the elliptic curve cryptography based key is that it is smaller than many other types of keys for the relative cryptographic strength. Further, it is possible, using elliptic curve algorithms, to store a random private key and compute the public key by a run-time computation.

Advantageously, especially considering the value of on-chip real estate, a compressed certificate can be provided in the non-volatile memory. Using a smaller data-set (than what would be required to store a device certificate) the device dynamically generates a certificate on the device, to provide to a requesting application. The device certificate may or may not be generated multiple times. For example, the device certificate could be generated once and stored in system external storage for further use. This is not particularly insecure because the certificate is public data.

A device constructed according to the technique may have applicability in other areas. For example, the device could be authenticated to a peer, or to any application that requires a first device certificate. In another alternative, the non-volatile memory may include a secure random number generator for the device, using the secure manufacturing process to program the non-volatile memory.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the inventions are illustrated in the figures. However, the embodiments and figures are illustrative rather than limiting; they provide examples of the invention.

FIG. 1 depicts an example of a system for validating a client at a server.

FIG. 2 depicts a flowchart of an example of a method for power up and power down of a device appropriate for use in the system.

FIG. 3 depicts a flowchart of an example of a method for generating a device certificate only once.

FIG. 4 depicts a computer system suitable for implementation of the techniques described above with reference to FIGS. 1-3.

FIG. 5 depicts an example of a secure system suitable for implementation of the techniques described above with reference to FIGS. 1-3.

FIG. 6 depicts a flowchart of an example of a method for manufacturing a secure device.

FIG. 7 depicts a flowchart of an example of a method for construction of a secure certificate.

DETAILED DESCRIPTION

In the following description, several specific details are presented to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or in combination with other components, etc. In other instances, well-known implementations or operations are not shown or described in detail to avoid obscuring aspects of various embodiments, of the invention.

FIG. 1 depicts an example of a system 100 for validating a client at a server. In the example of FIG. 1, the system 100 includes a server 102, a network 104, and a client 106. The server 102 includes a certificate request module 110, a certificate verification module 112, a Cert database 114, a pseudo-random number (PRN) generator 116, and an interface 118. The client 106 includes a certificate generation module 120, non-volatile (NV) memory 122, and an interface 124.

The server 102 may be any applicable known or convenient computer. The network 104 may be any communications network including, by way of example but not limitation, the Internet. The client 106 may be any applicable known or convenient computer that has secure storage. The NV memory 122 may include a secure key store and, in an embodiment, the NV memory 122 is on-chip memory.

In the example of FIG. 1, in operation, a protocol for registration or activation is initiated by the server 102. (The client 106 may, in an alternative, initiate the registration or activation.) In an embodiment, the protocol serves to register a device identity and certificate into the Cert database 114. To do so, the PRN generator 116 generates a PRN, R, and the certificate request module 110 of the server 102 generates a request for a device certificate. R and the request for a device certificate are sent via the interface 118 to the network 104.

R and the request for a device certificate are received at the interface 124 of the client 106. The certificate generation module 120 of the client 106 generates a certificate Cert. An example of the algorithm used to generate Cert is described with reference to FIG. 7, below. The certificate generation module 120 computes a signature Sig, over random number R, using a device private key. Operands are stored in the NV memory 122, which may reside in, for example, a secure kernel (see e.g., FIG. 5). In an alternative, the computation could include a device ID, serial number, region code, or some other value. The interface 124 of the client 106 returns R, any optional data, Cert, and Sig to the network 104.

The interface 118 receives at the server 102 R, any optional data, Cert, and Sig. The certificate verification module 112 at the server 102 validates Cert using a trusted certificate chain, validates Sig using Cert, and verifies that R is the same as the value, R, that was originally sent by the server 102 to the client 106. If successfully validated and verified, the server 102 imports Cert into the Cert database 114. At this point, the client 106 is presumably authorized to obtain from the server 102—or some other location that can use the certificate to authorize the client 106—digital licenses for rights managed content, and other operations.

In another embodiment, the device could generate a new key pair {pvt1,pub1} using a RNG, and a certificate could be created for the new public key pub1, using the device programmed private key as signer. This new key pvt1 could be used to sign the message having the random R.

It should be noted that secure networking protocols such as SSL and other services that require ephemeral secret keys typically make use of a source of a string of random numbers. A secure manufacturing process, such as is described by way of example but not limitation with reference to FIG. 6, below, can be used to seed a secret random number S in a device. A PRN generating algorithm using cryptographic primitives such as the functions in AES or SHA can be used to generate PRNs. The sequence should not repeat after power-cycle of the device. Using a state-saving mechanism involving the chip non-volatile memory ensures a high level of security. The device uses a part of re-writeable non-volatile memory to store a sequence number.

FIG. 2 depicts a flowchart 200 of an example of a method for power up and power down of a device appropriate for use in the system 100. In the example of FIG. 2, the flowchart 200 starts at module 202 where a device is powered on. In the example of FIG. 2, the flowchart 200 continues to module 204 where runtime state is initialized to 1. Since the runtime state is incremented over time, the runtime state should be stored in writable memory, such as on-chip writable memory.

In the example of FIG. 2, the flowchart 200 continues to module 206 where the device increments the sequence number and computes key=fn(S, sequence number), where S=a programmed secret seed random number. Since S is programmed, it can be stored in on-chip NV read-only memory (ROM). At this point, the device is presumed to be “up and running.”

In the example of FIG. 2, the flowchart 200 continues to module 208 where, in response to a request for a random number, the device generates random=fn(key, state) and increments state: state++. In the example of FIG. 2, the flowchart 200 continues to decision point 210 where it is determined whether another random number request is received. If it is determined that another random number request has been received (210-Y), then the flowchart 200 returns to module 208. In this way, module 208 may be repeated multiple times for multiple random number requests.

When it is determined there are no other random number requests (210-N), the flowchart 200 continues to module 212 where the device is powered off, and the state is lost. Thus, the flowchart 200 illustrates the state of the device from power on to power off. If the device is powered on again, a new key must be computed, and state initialized again.

FIG. 3 depicts a flowchart 300 of an example of a method for generating a device certificate only once. In the example of FIG. 3, the flowchart 300 starts at module 302 where a device certificate is generated at a secure device. The flowchart 300 continues to module 304 where the device certificate is stored in system external storage. This variation is notable because the device is secure, but the device certificate is public. Accordingly, the certificate is still secure, even though it is not regenerated each time.

FIG. 4 depicts a computer system 400 suitable for implementation of the techniques described above with reference to FIGS. 1-3. The computer system 400 includes a computer 402, I/O devices 404, and a display device 406. The computer 402 includes a processor 408, a communications interface 410, memory 412, display controller 414, non-volatile storage 416, and I/O controller 418. The computer 402 may be coupled to or include the I/O devices 404 and display device 406.

The computer 402 interfaces to external systems through the communications interface 410, which may include a modem or network interface. The communications interface 410 can be considered to be part of the computer system 400 or a part of the computer 402. The communications interface 410 can be an analog modem, ISDN modem, cable modem, token ring interface, satellite transmission interface (e.g. “direct PC”), or other interfaces for coupling a computer system to other computer systems. Although conventional computers typically include a communications interface of some type, it is possible to create a computer that does not include one, thereby making the communications interface 410 optional in the strictest sense of the word.

The processor 408 may include, by way of example but not limitation, a conventional microprocessor such as an Intel Pentium microprocessor or Motorola power PC microprocessor. While the processor 408 is a critical component of all conventional computers, any applicable known or convenient processor could be used for the purposes of implementing the techniques described herein. The memory 412 is coupled to the processor 408 by a bus 420. The memory 412, which may be referred to as “primary memory,” can include Dynamic Random Access Memory (DRAM) and can also include Static RAM (SRAM). The bus 420 couples the processor 408 to the memory 412, and also to the non-volatile storage 416, to the display controller 414, and to the I/O controller 418.

The I/O devices 404 can include a keyboard, disk drives, printers, a scanner, and other input and output devices, including a mouse or other pointing device. For illustrative purposes, at least one of the I/O devices is assumed to be a block-based media device, such as a DVD player. The display controller 414 may control, in a known or convenient manner, a display on the display device 406, which can be, for example, a cathode ray tube (CRT) or liquid crystal display (LCD).

The display controller 414 and I/O controller 418 may include device drivers. A device driver is a specific type of computer software developed to allow interaction with hardware devices. Typically this constitutes an interface for communicating with the device, through a bus or communications subsystem that the hardware is connected to, providing commands to and/or receiving data from the device, and on the other end, the requisite interfaces to the OS and software applications.

The device driver may include a hardware-dependent computer program that is also OS-specific. The computer program enables another program, typically an OS or applications software package or computer program running under the OS kernel, to interact transparently with a hardware device, and usually provides the requisite interrupt handling necessary for any necessary asynchronous time-dependent hardware interfacing needs.

The non-volatile storage 416, which may be referred to as “secondary memory,” is often a magnetic hard disk, an optical disk, or another form of storage for large amounts of data. Some of this data is often written, by a direct memory access process, into memory 412 during execution of software in the computer 402. The non-volatile storage 416 may include a block-based media device. The terms “machine-readable medium” or “computer-readable medium” include any known or convenient storage device that is accessible by the processor 408 and also encompasses a carrier wave that encodes a data signal.

The computer system 400 is one example of many possible computer systems which have different architectures. For example, personal computers based on an Intel microprocessor often have multiple buses, one of which can be an I/O bus for the peripherals and one that directly connects the processor 408 and the memory 412 (often referred to as a memory bus). The buses are connected together through bridge components that perform any necessary translation due to differing bus protocols.

Network computers are another type of computer system that can be used in conjunction with the teachings provided herein. Network computers do not usually include a hard disk or other mass storage, and the executable programs are loaded from a network connection into the memory 412 for execution by the processor 408. A Web TV system, which is known in the art, is also considered to be a computer system, but it may lack some of the features shown in FIG. 4, such as certain input or output devices. A typical computer system will usually include at least a processor, memory, and a bus coupling the memory to the processor.

The computer system 400 may be controlled by an operating system (OS). An OS is a software program—used on most, but not all, computer systems—that manages the hardware and software resources of a computer. Typically, the OS performs basic tasks such as controlling and allocating memory, prioritizing system requests, controlling input and output devices, facilitating networking, and managing files. Examples of operating systems for personal computers include Microsoft Windows®, Linux, and Mac OS®. Delineating between the OS and application software is sometimes rather difficult. Fortunately, delineation is not necessary to understand the techniques described herein, since any reasonable delineation should suffice.

The lowest level of an OS may be its kernel. The kernel is typically the first layer of software loaded into memory when a system boots or starts up. The kernel provides access to various common core services to other system and application programs.

As used herein, algorithmic descriptions and symbolic representations of operations on data bits within a computer memory are believed to most effectively convey the techniques to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussion, it is appreciated that throughout the description, discussions utilizing terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

An apparatus for performing techniques described herein may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, by way of example but not limitation, read-only memories (ROMs), RAMs, EPROMs, EEPROMs, magnetic or optical cards, any type of disk including floppy disks, optical disks, CD-ROMs, DVDs, and magnetic-optical disks, or any known or convenient type of media suitable for storing electronic instructions.

The algorithms and displays presented herein are not inherently related to any particular computer architecture. The techniques may be implemented using any known or convenient programming language, whether high level (e.g., C/C++) or low level (e.g., assembly language), and whether interpreted (e.g., Pert), compiled (e.g., C/C++), or Just-In-Time (JIT) compiled from bytecode (e.g., Java). Any known or convenient computer, regardless of architecture, should be capable of executing machine code compiled or otherwise assembled from any language into machine code that is compatible with the computer's architecture.

FIG. 5 depicts an example of a secure system 500 suitable for implementation of the techniques described above with reference to FIGS. 1-3. A typical secure system 500 may include a game console, media player, an embedded secure device, a “conventional” PC with a secure processor, or some other computer system that includes a secure processor.

In the example of FIG. 5, the secure system 500 includes a secure processor 502, an OS 504, ticket services 506, a calling application 508, and protected memory 510. In the example of FIG. 5, the OS 504 includes a security kernel 514, which in turn includes a key store 518, an encryption/decryption engine 517, and a security API 516. It should be noted that one or more of the described components, or portions thereof, may reside in the protected memory 510, or in unprotected memory (not shown).

It should further be noted that the security kernel 514 is depicted as residing inside the OS 504 by convention only. It may or may not actually be part of the OS 504, and could exist outside of an OS or on a system that does not include an OS. For the purposes of illustrative simplicity, it is assumed that the OS 504 is capable of authentication. In an embodiment, the ticket services 506 may also be part of the OS 504. This may be desirable because loading the ticket services 506 with authentication can improve security. Thus, in such an embodiment, the OS 504 is loaded with authentication and includes the ticket services 506.

For illustrative simplicity, protected memory is represented as a single memory. However protected memory may include protected primary memory, protected secondary memory, and/or secret memory. It is assumed that known or convenient mechanisms are in place to ensure that memory is protected. The interplay between primary and secondary memory and/or volatile and non-volatile storage is known so a distinction between the various types of memory and storage is not drawn with reference to FIG. 5.

The ticket services 506 may be thought of as, for example, “digital license validation services” and, in a non-limiting embodiment, may include known or convenient procedures associated with license validation. For example, the ticket services 506 may include procedures for validating digital licenses, PKI validation procedures, etc. In the example of FIG. 5, the ticket services 506 can validate a ticket from the calling application 508. In operation, the ticket services 506 obtains the ticket from the calling application 508, which proceeds to validate the ticket.

It is possible that the ticket is personalized. In that case, it could be decrypted using the device private key (programmed as discussed before) to compute a secret shared encryption key. The ticket may or may not be obtained using an Internet download mechanism and stored on rewritable flash memory.

In an embodiment, the security kernel 514 may be loaded at start-up. In another embodiment, a portion of the security kernel may be loaded at start-up, and the remainder loaded later. An example of this technique is described in application Ser. No. 10/360,827 entitled “Secure and Backward-Compatible Processor and Secure Software Execution Thereon,” which was filed on Feb. 7, 2003, by Srinivasan et al., and which is incorporated by reference. Any known or convenient technique may be used to load the security kernel 514 in a secure manner.

The key store 518 is a set of storage locations for keys. The key store 518 may be thought of as an array of keys, though the data structure used to store the keys is not critical. Any applicable known or convenient structure may be used to store the keys. In a non-limiting embodiment, the key store 518 is initialized with static keys, but variable keys are not initialized (or are initialized to a value that is not secure). For example, some of the key store locations are pre-filled with trusted values (e.g., a trusted root key) as part of the authenticated loading of the security kernel 514. The private key in the non-volatile memory could be retrieved and stored in the keystore for future use.

The encryption/decryption engine 517 is, in an embodiment, capable of both encryption and decryption. For example, in operation, an application may request of the security API 516 a key handle that the application can use for encryption. The encryption/decryption engine 517 may be used to encrypt data using the key handle. Advantageously, although the security API 516 provides the key handle in the clear, the key itself never leaves the security kernel 514.

The security API 516 is capable of performing operations using the keys in the key store 518 without bringing the keys out into the clear (i.e., the keys do not leave the security kernel 514 or the keys leave the security kernel 514 only when encrypted). The security API 516 may include services to create, populate and use keys (and potentially other security material) in the key store 518. In an embodiment, the security API 516 also provides access to internal secrets and non-volatile data, including secret keys and device private key. For example, the device private key might be stored in the keystore and used by the security API. One API call could be used to return a device certificate (using an algorithm discussed herein to generate the certificate). Another API call can be constructed to use the private key to compute a shared key for decryption, or use the private key to sign a message or certificate. Depending upon the implementation, the security API 516 may support AES and SHA operations using hardware acceleration.

In the example of FIG. 5, the ticket services 506 and the security API 516 may execute in a separate execution space for system security. In order to validate data blocks, the ticket services 506 may validate the ticket using data in the header. The ticket may include an encrypted key. The ticket services 506 decrypts the key using services in the security kernel 514 (e.g., the encryption/decryption engine 517).

In an embodiment, the encryption/decryption engine 517 uses secret common keys from the key store 518 to perform this decryption. In another embodiment, the ticket services 506 could use a device personalized ticket obtained from flash or network (not shown), validate some rights to content, and then return the key. In any case, this process returns the key. The personalized ticket could be encrypted by a key that is a function of the device private key, programmed in the non-volatile memory.

An example of data flow in the system 500 is provided for illustrative purposes as arrows 520-528. Receiving the certificate request at the ticket services 506 is represented by a certificate request arrow 520 from the calling application 508 to the ticket services 506.

Forwarding the certificate request from the ticket services 506 to the security API 516 is represented by a certificate request arrow 522. Within the security kernel 514, the public key/device certificate construction engine 517 accesses keys/signature data from the key/signature store 518. The access is represented by the private key/signature access arrow 524. The security API 516 returns a device certificate to the ticket services 506, as represented by the device certificate arrow 526, which is forwarded to the calling application 508, as represented by the device certificate arrow 528.

FIG. 6 depicts a flowchart 600 of an example of a method for manufacturing a secure device. This method and other methods are depicted as serially arranged modules. However, modules of the methods may be reordered, or arranged for parallel execution as appropriate. In the example of FIG. 6, the flowchart 600 begins at module 602 where a device ID is obtained. The device ID may be a serial number or some other unique identifier for the device.

In the example of FIG. 6, the flowchart 600 continues to module 604 where a pseudo-random number is provided for use as a small-signature private key for the device. To date, truly random numbers are not generable on a computer; of course, a pseudo-random number generator or an external secured hardware true random number generator could work for the intended purpose. A small-signature private key may be, by way of example but not limitation, an elliptic curve private key, or some other private key with a relatively small footprint.

In the example of FIG. 6, the flowchart 600 continues to module 606 where a public key is computed from the private key using common parameters. For example, a multiple of a base point may be computed, where a scalar multiple is the private key.

In the example of FIG. 6, the flowchart 600 continues to module 608 where a fixed certificate structure is used to construct a certificate. The certificate is signed using a small signature algorithm such as elliptic curve DSA. In an embodiment, the fixed certificate structure may include at least the device ID, issuer name, and device public key. A small-signature algorithm is used to minimize the size of the signature. By way of example but not limitation, an elliptic curve signature algorithm may be used.

In the example of FIG. 6, the flowchart 600 continues to module 610 where {device ID, private key, issuer ID, signature} is programmed into the non-volatile memory of the device. This set includes these four items because the items provide sufficient security for most purposes, and the set has a relatively small footprint due to the relatively small size of the private key and signature. (The device ID and issuer ID also, presumably, have relatively small footprints.) In an embodiment, any other data that is needed to construct the device certificate such as the public key may be generated programmatically on demand. However, more items could be programmed into the non-volatile memory, or fewer, as appropriate for a given embodiment or implementation.

In the example of FIG. 6, the flowchart 600 continues to module 612 where a secret random number is programmed into the ROM of the device. The secret random number may be pseudo-randomly generated or arbitrarily assigned. This secret random number can be used to support secure pseudo-random number generation. In an alternative, the ROM may be replaced with some other known or convenient NV storage.

FIG. 7 depicts a flowchart 700 of an example of a method for construction of a secure certificate. Advantageously, the method enables the device having the non-volatile programmed key and required software to construct a full device certificate that can be used to validate the device. In the example of FIG. 7, the flowchart 700 starts at module 702 where a request for a device certificate is received from a calling application.

In the example of FIG. 7, the flowchart 700 continues to module 704 where {device ID, private key, issuer ID, signature} is read from non-volatile memory. In an embodiment, a security kernel module accesses and reads the non-volatile memory. An example of a security kernel module that is appropriate for this purpose is described in U.S. patent application Ser. No. 10/360,827 entitled “Secure and Backward-Compatible Processor and Secure Software Execution Thereon,” which was filed on Feb. 7, 2003, by Srinivasan et al., and/or in U.S. patent application Ser. No. 11/586,446 entitled “Secure Device Authentication System and Method,” which was filed on Oct. 24, 2006, by Srinivasan et al., both of which are incorporated by reference. However, any applicable known or convenient security kernel module could be used.

In the example of FIG. 7, the flowchart 700 continues to module 706 where the public key is computed from the private key and common parameters, if any. In an embodiment, the computation makes use of the same algorithm that was used in a manufacturing process, such as the method described with reference to FIG. 6, above. The public key may be computed in a security kernel.

In the example of FIG. 7, the flowchart 700 continues to module 708 where a device certificate is constructed from device ID, issuer ID, public key, signature, and common parameters. In an embodiment, a security kernel module is aware of the structure of the device certificate, as is used in a manufacturing process, such as the method described with reference to FIG. 6, above. Advantageously, the device certificate can be constructed on demand.

In the example of FIG. 7, the flowchart 700 continues to module 710 where the device certificate is provided to the calling application. The flowchart 700 ends when the device certificate is provided to the calling application. The method could be started again by another calling application (or by the same calling application if, for some reason, the device certificate was needed again.)

As used herein, the term “content” is intended to broadly include any data that can be stored in memory.

As used herein, the term “embodiment” means an embodiment that serves to illustrate by way of example but not limitation.

It will be appreciated to those skilled in the art that the preceding examples and embodiments are exemplary and not limiting to the scope of the present invention. It is intended that all permutations, enhancements, equivalents, and improvements thereto that are apparent to those skilled in the art upon a reading of the specification and a study of the drawings are included within the true spirit and scope of the present invention. It is therefore intended that the following appended claims include all such modifications, permutations and equivalents as fall within the true spirit and scope of the present invention.

Claims

1. A device comprising: a secure processor having secure cryptography hardware implemented thereon;a secure on-chip non-volatile (NV) memory coupled to the secure processor, the secure on-chip NV memory having a security kernel receiving instructions from the secure processor, the security kernel containing: a private key datastore configured to store a rewritable state and a device private key based at least in part on a programmed secret seed and the rewritable state, the device private key being part of a cryptographic key pair comprising a public key associated with the device private key, and the rewritable state being a state of a secure application encrypted with the public key;an authenticated security Application Programming Interface (API) coupled to the private key datastore, the authenticated security API configured to provide one or more instructions to gather the device private key from the private key datastore;a certificate construction engine coupled to the authenticated security API, the certificate construction engine configured to use the device private key to generate a device certificate, the device certificate providing the device with access to the secure application.

2. The device of claim 1, wherein the programmed secret seed comprises a pseudorandom number.

3. The device of claim 1, wherein the programmed secret seed is stored on on-chip read-only memory (ROM) coupled to the secure processor.

4. The device of claim 1, wherein the security kernel uses the programmed secret seed and the rewritable state to generate the device private key.

5. The device of claim 1, wherein the cryptographic key pair comprises an elliptical cryptographic key pair.

6. The device of claim 1, wherein the security kernel identifies the public key in response to a request to execute the secure application.

7. The device of claim 1, wherein the device private key comprises a variable key.

8. The device of claim 1, wherein the certificate construction engine uses the device private key to generate the device certificate in response to a request to validate an electronic ticket provided by the secure application.

9. The device of claim 1, wherein the secure processor loads the security kernel into the secure on-chip NV memory in response to a start-up of the device.

10. The device of claim 1, wherein the device comprises a game console or a media player.

11. A method executed by a secure processor having secure cryptography hardware implemented thereon, the method executed in a security kernel of a secure on-chip non-volatile (NV) memory coupled to the secure processor, the method comprising: storing a rewritable state and a device private key based at least in part on a programmed secret seed and the rewritable state, the device private key being part of a cryptographic key pair comprising a public key associated with the device private key, and the rewritable state being a state of a secure application encrypted with the public key;providing one or more instructions to gather the device private key from a private key datastore;using the device private key to generate a device certificate, the device certificate providing a device with access to the secure application.

12. The method of claim 11, wherein the programmed secret seed comprises a pseudorandom number.

13. The method of claim 11, wherein the programmed secret seed is stored on on-chip read-only memory (ROM) coupled to the secure processor.

14. The method of claim 11, wherein the security kernel uses the programmed secret seed and the rewritable state to generate the device private key.

15. The method of claim 11, wherein the cryptographic key pair comprises an elliptical cryptographic key pair.

16. The method of claim 11, wherein the security kernel identifies the public key in response to a request to execute the secure application.

17. The method of claim 11, wherein the device private key comprises a variable key.

18. The method of claim 11, wherein using the device private key to generate the device certificate comprises using the device private key to generate the device certificate in response to a request to validate an electronic ticket provided by the secure application.

19. The method of claim 11, wherein the secure processor loads the security kernel into the secure on-chip NV memory in response to a start-up of the device.

20. The method of claim 11, wherein the secure processor and the secure on-chip NV memory are incorporated into a game console or a media player.