In an ideal environment, an electrical signal applied to a driven end of a signal line would instantaneously propagate to a receiving end of the signal line, and graphs of the electrical signal obtained from the driven and receiving ends of the signal line would be the same. In the real world, however, this does not occur. In addition to the inherent delay that is imparted to an electrical signal as a result of the impedance of the signal line over which it propagates, the propagation of an electrical signal is influenced by a host of physical and environmental factors, such as manufacturing variance, line coupling (e.g., capacitive and inductive coupling to adjacent signal lines), radio frequency (RF) and microwave interference, and temperature. These factors may variously result in signal delay, signal skew or signal noise.
One aspect of the invention is embodied in a method that comprises driving a dynamic signal onto a driven end of a first signal line, and driving an ungrounded bias signal onto a driven end of a second signal line. The ungrounded bias signal is then received at a receiving end of the second signal line, and the dynamic signal is received at a receiving end of the first signal line. The receiving end of the second signal line is coupled to a first input of a quasi-differential receiver, and the receiving end of the first signal line is coupled to a second input of the receiver. The ungrounded bias signal is used to bias a toggle point of the receiver, and the dynamic signal is used to toggle an output of the receiver.
Another aspect of the invention is embodied in apparatus comprising a receiver, first and second signal lines, a dynamic signal driver, and an ungrounded bias signal driver. The receiver has first and second transistors that are coupled to an output node to respectively pull the output node to first and second voltages. The first and second signal lines are respectively coupled to the first and second transistors. The dynamic signal driver is coupled to the first signal line; and the ungrounded bias signal driver is coupled to the second signal line.
Other embodiments of the invention are also disclosed.
Illustrative and presently preferred embodiments of the invention are illustrated in the drawings, in which:
The ungrounded bias signal (or “driver-side” bias) disclosed above provides a partially floating bias that, in turn, can provide at least some common-mode noise rejection for the dynamic signal transmitted over the signal line 202.
Each of the signal lines 202, 208, 218 shown in
In one embodiment of the method 100, the first and second signal lines 202, 208 are routed adjacent and substantially parallel to each other. In this manner, the second signal line 208 provides electromagnetic shielding for the first signal line 202 (i.e., the line over which the dynamic signal propagates). Optionally, a third signal line 216 may be routed adjacent and substantially parallel to the first signal line 202, opposite a side of the first signal line on which the second signal line 208 runs. The method 100 may then comprise driving the ungrounded bias signal onto a driven end 218 of the third signal line; receiving the ungrounded signal at a receiving end 220 of the third signal line 216 (the receiving end 220 of the third signal line 216 being coupled to the first input of the receiver 214); and routing the third signal line 216 adjacent and substantially parallel to the first signal line 202, opposite a side of the first signal line on which the second signal line 208 runs. In this manner, the first, second and third signal lines 202, 208, 216 form a quasi-coax signal line structure. Signal lines carrying the same or different ungrounded bias signal could also be routed above and below the first signal line 202.
In another embodiment of the method 100, the voltage swing of the first signal line 202 is clamped in proximity to its receiving end 206, thereby limiting the range of voltages allowed at the signal line's receiving end 206 to a range of voltages that is smaller than a range of voltages allowed at the driven end 204 of the signal line 202. Such a voltage clamping method is taught in the U.S. Pat. No. 6,351,171 of Balhiser entitled “Accelerated Interconnect Transmission via Voltage Clamping Toward Toggle Point”. As shown in
As further shown in
In the circuit 300, each of the voltage clamps 222, 224 proximate to the receiver 214 is implemented as a diode-connected NFET 306, 308. By means of the NFETs 306, 308, the voltage at the receiver 214 is prevented from reaching either of voltages VDD or GND. By limiting the voltage swing of the dynamic signal received by the receiver 214, charge on the line 202 can be limited, and dynamic signals can propagate through the circuit 300 more quickly. Although both of the voltage clamps 222, 224 are optional, one variant of the circuit 300 utilizes only the clamp 222, but not the clamp 224.
The bias driver 228 is implemented in the circuit 300 using first and second transistors 310, 312 that are coupled to the driven end 210 of line 208 similarly to how the transistors 302, 304 of the dynamic signal driver 226 are coupled to the line 202. However, the gate of the PFET 310 is tied to ground (GND), and the gate of the NFET 312 is tied to the voltage VDD. The transistors may be variously sized, and the ratio of their drive strengths may be adjusted, to adjust the toggle point of the receiver 214. Furthermore, the transistors' drive strengths may be scaled to adjust the output impedance of the driver 226. As previously mentioned, increasing the impedance will allow more float of line 208, while decreasing the impedance will provide more shielding for line 202.
The receiver 214 is implemented by means of first and second NFETs 314, 316, each of which is coupled to the output node O4 to respectively pull the output node to GND or VDD. The first and second signal lines 202, 208 are respectively coupled to the NFETs 314, 316. Coupled in parallel with the NFET 316 is a resistor R0. The resistor R0 is also used to bias the toggle point of the receiver 214. In one embodiment, the resistor R0 is used to provide a substantially stronger bias to the output node O4 than the NFET 316 (e.g., by a 90:10 ratio). However, the ratio of bias provided by the two devices 316, R0 can be adjusted to suit a given application of the circuit 300. Increasing the value of resistor R0 lowers the toggle point of the receiver 214, but lowering the value of resistor R0 allows signal edges at node O4 to rise faster. Also, the ratio of drive strengths between NFET 314 and NFET 316 may be adjusted. In one embodiment, the drive strength of NFET 314 is substantially stronger than the drive strength of NFET 316.
Given the clamped voltage swing at the receiving end 206 of the line 202, output node O4 may be coupled to an inverting and amplifying buffer 318, 320 that provides output OUT4.
In one embodiment, the circuit 300 may be used in conjunction with the circuit modifications taught in U.S. patent application Ser. No. 10/728,604 of Balhiser entitled “Driver-Side Current Clamping with Non-Persistent Charge Boost” (filed Dec. 5, 2003).
While illustrative and presently preferred embodiments of the invention have been described in detail herein, it is to be understood that the inventive concepts may be otherwise variously embodied and employed, and that the appended claims are intended to be construed to include such variations, except as limited by the prior art.
Number | Name | Date | Kind |
---|---|---|---|
3453447 | Campanella | Jul 1969 | A |
4066918 | Heuner et al. | Jan 1978 | A |
4630284 | Cooperman | Dec 1986 | A |
4760433 | Young et al. | Jul 1988 | A |
4952916 | Taplin | Aug 1990 | A |
5444751 | Sage | Aug 1995 | A |
5525933 | Matsuki et al. | Jun 1996 | A |
5574395 | Kusakabe | Nov 1996 | A |
5656873 | O'Loughlin et al. | Aug 1997 | A |
5781028 | Decuir | Jul 1998 | A |
5825240 | Geis et al. | Oct 1998 | A |
5880621 | Ohashi | Mar 1999 | A |
6201405 | Hedberg | Mar 2001 | B1 |
6351171 | Balhiser | Feb 2002 | B1 |
6600339 | Forbes et al. | Jul 2003 | B1 |
6670830 | Otsuka et al. | Dec 2003 | B1 |
6704365 | Haycock | Mar 2004 | B1 |
6822498 | Schroeder et al. | Nov 2004 | B1 |
6852613 | Forbes et al. | Feb 2005 | B1 |
Number | Date | Country | |
---|---|---|---|
20050264326 A1 | Dec 2005 | US |