The present disclosure relates to maintaining security of operations performed in a computing device.
The number of controllers in computing devices has recently increased dramatically. Controllers included in computing devices are currently used to control and measure parameters such as fan speed, memory configuration and voltage settings. Unfortunately, as the number of functions controlled by these devices increases, so too does the associated security threat. For example, a malicious party may take over a computing device and issue unauthorized commands to one or more of the controllers in the computing device, damaging, or possibly destroying, the device itself. In certain deployments, such as government and financial networks, for example, such threats may lead to costly damages, or worse. However, enforcing policies inside a computing device can be difficult, particularly if a malicious party has gained control of a processor or software inside the computing device.
Overview
In accordance with one embodiment, a computing device includes a first component, a second component and a third component that is also referred to as a monitoring component. The monitoring component, receives, from the first component, a command to issue one or more transactions or data to the second component, and determines whether the first component is authorized to issue the one or more transactions, according to one or more policies or rules, which are received through an out-of-band (OOB) mechanism to which the first component does not have access. If the monitoring component determines that the first component is authorized to issue the one or more transactions or data to the second component, it forwards the one or more transactions or data to the second component. Otherwise, the monitoring component blocks the one or more transactions or data from being issued to the second component.
With reference first to
The one or more processors 115 may be a microprocessor or a microcontroller. It should be understood, however, that processor 115 may be any component and/or device configured to issue commands and/or data over any communication channel or medium. For example, processor 115 may be one or more networks, one or more controlled buses, one or more interfaces or one or more controllers.
It should be further understood that monitoring component 130 may be any suitable programmable device, such as an application specific integrated circuit (“ASIC”), a field-programmable gate array (“FPGA”), or any such immutable device, e.g., a solid-state device having Read-Only Memory (“ROM”), that is capable of receiving policies or rules from an external device through an OOB mechanism. Accordingly, monitoring component 130 may be any component or device that is configured to determine whether to forward transactions and/or data received from a first component or device to a second component or device based on a set of policies or rules received through an OOB mechanism to which the first component does not have access.
The system 100 further includes a controller 180 that can communicate with the computing device 110 via link 185 or a network 190. Network 190 may include one or more wide area networks (WANs), such as the Internet, and one or more local area networks (LANs). The system may optionally include an external memory device 195 that may store OOB control information that may be communicated to monitoring component 130. For example, monitoring component 130 may be a field programmable gate array (“FPGA”) and memory device 195 may store FPGA programming code that is loaded onto monitoring component 130 when computing device 110 is initially powered-up.
The memory 120 may include read only memory (ROM), random access memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical, or other physical/tangible memory storage devices that stores executable instructions for an operating system 122 and for one or more software applications 124. Thus, in general, memory 120 may include one or more tangible (non-transitory) computer readable storage media (e.g., a memory device) encoded with software comprising computer executable instructions and when the software is executed (by processor 115) it is operable to perform the operations of computing device 110, which provides a platform on which the operating system 122 and one or more software applications 124 stored in memory 120 may be executed by processor 115.
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As shown in
Although shown in
Computing device 110 may be a wired or wireless communication device and may operate in accordance with any communication/network technology, including, but not limited to, Ethernet, Wi-Fi®, Bluetooth®, 4G or LTE, etc. For example, computing device 110 may be a laptop, tablet, smartphone, etc. In still another example, the computing device 110 may be a network device, such as a router, switch, firewall, gateway, etc. Controller devices 140(1)-140(N) may be any device that monitors and/or controls various functions and/or devices in computing device 110 and each is responsive to commands received from processor 115 via bus 160 and filtered bus 170. For example, the controller devices 140(1)-140(N) may include a voltage regulator that controls/monitors the power supply in computing device 110, a temperature regulator that controls fan speeds in computing device 110, etc. A controller device 140(1)-140(N) may be an Inter-Integrated Circuit (I2C) device that may have its own registers, memory and an executable command set.
In operation, processor 115 executes operating system 122 and/or one or more applications 124, and, in response to a request received from operating system 122 and/or or one or more software applications 124, generates a command to monitoring component 130 to initiate/issue one or more transactions to one or more specified controller devices 140(1)-140(N) and places the command on bus 160. In response to receiving the command from processor 115, monitoring component 130 determines whether processor 115 is authorized to issue the one or more transactions on the bus. For example, monitoring component 130 may confirm that each of the one or more transactions is included in an access list, i.e., a “white” list, of commands that processor 115 is authorized to issue, or may confirm that none of the one or more transactions is included in a “black” list of commands that processor 115 is expressly prohibited from issuing. According to an embodiment, processor 115 may encrypt the command including the one or more transactions with a private encryption key uniquely associated with processor 115. Monitoring component 130 may then decrypt the encrypted command using a public encryption key associated with processor 115, thereby authenticating processor 115 and validating the one or more transactions. According to a further embodiment, monitoring component 130 may confirm that processor 115 is authorized to issue a command by checking predefined policies that may include a list of conditions and/or events under which processor 115 is authorized to issue specific commands. For example, processor 115 may be allowed to issue a read voltage value command, but may not issue a write voltage value command. Further examples of policy-based rules may include that processor 115 is allowed to issue read commands only within a predefined period after computing device 110 has powered on, or that processor 115 is allowed to issue any command provided that processor 115 provides an appropriate cryptographic key to monitoring component 130. According to an embodiment, monitoring component 130 may notify network controller 180 if processor 115 attempts to issue any unauthorized commands or may seek approval from network controller 180 if processor 115 issues any commands that are defined as highly sensitive, e.g., processor 115 seeks to change the voltage on a power rail in computing device 110.
It should be understood that monitoring component 130 may be required to authorize every command to issue one or more transactions received from processor 115 before issuing the one or more transactions on filtered bus 170. Therefore, even if headers are required to program a component/device in computing device 110 during manufacturing, the authentication mechanism described herein may implemented to ensure that the required headers associated with the one or more components/devices in computing device 110 may not be used to bypass the authentication protections provided by monitoring component 130.
In deployments such as those shown in
Generally, a controller 180 initially defines the rules and policies to be enforced by a monitoring component 130, authorizing the commands that processor 115 may issue to one or more controller devices 140(1)-140(N) in computing device 110. Therefore, to issue one or more transactions to one or more controller devices 140(1)-140(N), processor 115 sends a command to monitoring component 130 requesting that monitoring component 130 issue the one or more transactions included in the command to the one or more controller devices 140(1)-140(N). If monitoring component 130 determines that processor 115 is authorized to issue the one or more transactions, monitoring component 130 will issue the one or more transactions to the one or more controller devices 140(1)-140(N) on filtered bus 170. If, however, monitoring component 130 determines that processor 115 is not authorized to issue the one or more transactions, monitoring component 130 will block the one or more transactions from being issued on filtered bus 170. Optionally, monitoring component 130 may send an alarm signal to controller 180 if it determines that processor 115 is not authorized to issue the one or more transactions, alerting controller 180 that processor 115 has issued an unauthorized command.
As discussed in greater detail below, controller 180 may be a stand-alone computer or a server running one or more applications responsible for controlling the operations of one or more monitoring components 130 in one or more computing devices 110. Alternatively, controller 180 may be an application running in a cloud/data-center environment.
Reference is now made to
Control logic 230 includes instructions for determining whether processor 115 is authorized to issue one or more commands, including one or more transactions, to one or more controller devices 140(1)-140(N). As discussed above, the monitoring component 130 in its entirety or portions thereof may be implemented in, or be performed by, any suitable programmable device, such as an application specific integrated circuit (“ASIC”), a field-programmable gate array (“FPGA”), or any such immutable device, e.g., a solid-state device having Read-Only Memory (“ROM”), which may be desirable for function as well as cost. For example, the monitoring component 130 could be part of an existing FPGA used in the computing device (such as a secure boot device) or as a stand-alone device similar to an Inter-Integrated Circuit multiplexer.
Access control list 240 may include a list of specific commands that processor 115 is authorized to issue, and/or a list of specific commands that processor 115 is not authorized to issue, to the one or more controller devices 140(1)-140(N). Optionally, access control list 240 may further include key store 250 which may store public cryptographic keys associated with processor 115, enabling monitoring component 115 to authenticate one or more commands received from processor 115. Policy and rules database 260 stores conditions and/or events under which processor 115 may, or may not, be authorized to issue one or more specific commands. It should be understood that access control list 240 and policy and rules database 260 may identify commands that processor 115 is authorized to issue, and/or not authorized to issue, for each individual controller device 140(N). It should be further understood that controller 180 or external memory 195 may initially populate and/or dynamically modify the authorized commands included in access control list 240 and the policies associated with processor 115 included in policy and rules database 260. Processor 210 may execute instructions for control logic 230. For example, processor 210 may execute instructions causing control logic 230 to determine whether processor 115 is authorized to issue one or more commands on filtered bus 170. It should be understood that, while
Referring again to
Reference is now made to
Reference is now made to
Reference is now made to
The one or more processors 410 may be a microprocessor or a microcontroller. The memory 420 may include read only memory (ROM), random access memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical, or other physical/tangible memory storage devices. Thus, in general, memory 420 may include one or more tangible (non-transitory) computer readable storage media (e.g., a memory device) encoded with software comprising computer executable instructions and when the software is executed (e.g., by processor 410) it is operable to perform the operations of the controller 180 described herein.
Controller software 430 may include instructions enabling controller 180 to manage the operations of the monitoring component 130 in each of one or more computing devices 110(1)-110(N) by sending out-of-band control information to the monitoring component 130 in the respective one or more computing devices 110(1)-110(N), thereby providing the monitoring component 130 with rules that define when the processor 115 in the respective computing device 110 is authorized to issue one or more commands to filtered bus 170. For example, controller software 430 may send an instruction to a monitoring component 130 of a computing device 110 requiring that the monitoring component 130 prevent an associated processor 115 from issuing a write/set command to a sensitive voltage rail inside a computing device 110. It should be understood that controller software 430 may further include instructions for initially populating and/or dynamically modifying the rules to be enforced by the monitoring component 130 in each of the one or more computing devices 110(1)-110(N). Controller software 430 may further include instructions for processing alerts received from the monitoring component 130 of the one or more computing devices 110, which alerts may indicate that the processor 115 in a computing 110 device has attempted to issue one or more unauthorized commands.
Controller 180 may optionally include key store 440, which may store public cryptographic keys associated with the one or more processors 115 in each of the one or more computing devices 110(1)-110(N), enabling each of the one or more associated monitoring components 130 to authenticate one or more commands received from the one or more processors 115. Policy and rules database 450 may store rules under which, for a given condition and/or event, one or more processors 115 may, or may not, be authorized to issue one or more specific commands to the filtered bus 170 in the computing device and ultimately to one or more associated controllers 140(1)-140(N). Policy and rules database 450 may further identify specific commands that the processor 115 in a computing device 110 is authorized to issue, and/or not authorized to issue, for each associated controller device 110. Processor 410 may execute instructions for controller module 430. For example, processor 410 may execute instructions causing controller module 430 to send out-of-band control information to a monitoring component 130 of a computing device 110 enabling the monitoring component 130 to determine whether an associated processor 115 is authorized to issue one or more commands to filtered bus 170.
With reference to
At 510, monitoring component 130 receives from a first component a command to issue one or more transactions or data to a second component. At 520, monitoring component 130 determines whether the first component is authorized, according to one or more policies or rules, to issue the one or more transactions or data to the second component, wherein the one or more policies or rules are received using an out-of-band (OOB) mechanism to which the first component does not have access.
If the monitoring component 130 determines that the first component is authorized to issue the one or more transactions or data, operations proceed to 550, otherwise, at 540, monitoring component 130 blocks the received command, thereby preventing the one or more transactions or data from being issued to the second component, and method 500 ends. According to an alternative embodiment, at 540, monitoring component 130 may further send an alert signal to controller 180 reporting that monitoring component 130 has intercepted and blocked an unauthorized command to issue one or more transactions or data.
At 550, monitoring component 130 issues the one or more transactions or data included in the received command to the second component, and method 500 ends.
The embodiments presented herein verify and/or monitor commands to issue transactions or data to devices that control critical system functionality of a computing device. An out-of-band mechanism is provided that only allows commands that a programmer or other authorized or trusted person or entity has approved to be safe, while other commands are blocked and/or reported.
The embodiments disclosed herein allow an external controller entity or application to securely define, via an out-of-band mechanism, the commands that a processor is authorized to issue to one or more controller devices in a computing device, as well as to securely define the commands that a processor is not authorized to issue to one or more controller devices in a computing device. Similarly, the embodiments disclosed herein also allow a controller to securely define the conditions and/or events under which a processor is authorized, or not authorized, to issue specific commands to one or more controller devices in a computing device. For example, a processor may be authorized to read voltage values associated with a power rail in the computing device, but may be prevented from setting the voltage values associated with the power rail. The access lists and/or policy and rules database may be initially defined, or subsequently modified, only by an administrator through an out-of-band link to a monitoring component that monitors every transaction issued by the one or more processors in the computing device. The one or more processors are, therefore, unable to modify the access lists and/or policy-based rules applied by the monitoring component. Optionally, the monitoring component may be required to cryptographically authenticate the processor before the processor is authorized to issue any transactions on the internal bus. As a result, the integrity of internal bus transactions is securely preserved, ensuring that only authorized transactions are issued onto the internal bus. Furthermore, if the monitoring device detects an unauthorized transaction, it may send an alarm signal to the controller, alerting the controller that the computing device may be compromised, thereby preserving the integrity of the computing device and, potentially, other computing devices within the same network.
Advantages of the embodiments include providing an additional layer of security to control/restrict the ability of third parties to maliciously attack a computing device by gaining control of one or more processors in the computing device. In certain deployments, such as government and financial institutions, there is a requirement that computing devices provide secure and continuous services. Thus, the monitoring component referred to herein may be deployed in certain environments where this additional layer of security is desired. According to embodiments presented herein, a processor may only issue one or more transactions on an internal bus if a network controller has previously authorized the processor to issue the one or more transactions and/or the monitoring component cryptographically authenticated the processor. In so doing, the monitoring component described herein may verify that a processor is authorized to issue one or more transactions before placing the one or more transactions onto an internal bus connected to one or more controller devices, thereby preventing a malicious attacker from damaging, destroying or even taking control over the computing device.
In accordance with one embodiment, a method and system are disclosed in which a monitoring component, using stored data, validates a command for one or more transactions or data to one or more controller devices prior to issuing the one or more transactions on an internal bus. The stored data may be initially defined, or subsequently modified, only by an external controller, via an out-of-band mechanism to the monitoring component. In so doing, only the controller is able to determine the transactions that the one or more processors in a computing device are authorized to issue. As such, the out-of-band mechanism prevents a malicious attacker from using the processor to corrupt the data stored in the monitoring component, ensuring the integrity of the internal bus.
In one form, a method is provided comprising: in a computing device: receiving, from a first component, a command to issue one or more transactions or data to a second component; determining whether the one or more transactions or data are authorized according to one or more policies or rules, wherein the one or more policies or rules are received using an out-of-band mechanism to which the first component does not have access; and if it is determined that the one or more transactions or data are authorized, forwarding the one or more transactions or data to the second component, and otherwise, blocking the one or more transactions or data.
In another form, an apparatus is provided comprising: a first component; second component; and a monitoring component coupled to the first component and to the second component, and configured to: receive from the first component a command to issue one or more transactions or data to the second components; determine whether the one or more transactions or data are authorized according to one or more policies or rules, wherein the one or more policies or rules are received using an out-of-band mechanism to which the first component does not have access; and if it is determined that the one or more transactions or data are authorized, forward the one or more transactions or data to the second component, and otherwise, block the one or more transactions or data.
In yet another form, a non-transitory computer readable storage media storing executable instructions that are operable in a computing device, to perform operations to: receive from a first component a command to issue one or more transactions or data to a second component; determine whether the one or more transactions or data are authorized according to one or more policies or rules, wherein the one or more policies or rules are received using an out-of-band mechanism to which the first component does not have access; and if it is determined that the one or more transactions or data are authorized, forward the one or more transactions or data to the second component, and otherwise, block the one or more transactions or data.
The above description is intended by way of example only. Various modifications and structural changes may be made therein without departing from the scope of the concepts described herein and within the scope and range of equivalents of the claims.
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