Patent Application
20150305128
The present invention relates generally to lighting ballasts. More particularly, the present invention relates to detecting arcing condition within a ballast current loop.
Arcing is the electrical breakdown of a gas that produces an ongoing discharge resulting from a current flowing through a normally non-conductive media, such as air. In lamp systems, arcing often occurs when there is a small air gap between the terminals that electrically connect a lamp to an electronic ballast. For example, a small air gap is often created between ballast connector terminals and lamp pins when the lamp is removed from the ballast.
The occurrence of arcing in lamp systems can seriously damage the ballast and the lamp, as well as pose a hazard to safety. Arcing, particularly when prolonged, can result in a deposition of carbon at he ballast connector terminals, which can cause flashover of the ballast connector terminals and the lamp pins. These conditions can cause the ballast to malfunction or start a fire.
Unfortunately, arcing in ballasts can be difficult to detect. Conventional methods often detect arcing conditions at the lamp load, making it difficult to prevent or extinguish the arcing condition without recycling the power to the load.
Given the aforementioned deficiencies, a need exists for a more reliable ballast system. that is capable of detecting arcing conditions within the current loop such that arcing conditions can be eliminated or reduced before reaching the load. More specifically, a need exists for systems and techniques for detecting arcing in current loops to prevent or extinguish the arcing condition without having to recycle the power to the load.
In an exemplary embodiment, a method to detect an arcing condition in an arc discharge lamp ballasts is disclosed. An alternating current (AC) signal flows through a current loop and is used to drive a lamp load. The AC signal flows from the lamp load to ground via at least one ring core. The ring core is provided for detecting an arcing condition in AC signal and the ballast circuit by detecting a current spike along the ring core.
When a current spike is present in the primary core, created by the arcing condition; a proportional increase in voltage within a control signal occurs on the secondary core. A rectifier circuit is used for conditioning the increase in voltage within the control signal. A control circuit, responsive to the increase in voltage within the control signal, dynamically adjusts the operating frequency of a resonant inverter so that the arcing condition is extinguished.
In an embodiment, the magnitude of the control signal during normal operation is zero. In a further embodiment, the control signal can be used to control the inverter operating frequency, so that the high frequency bus voltage can be driven lower to eliminate arcing. The arcing conditions can be detected through the ground line when arcing happens by inserting a ring core or any other type of transformers into the ground line. The arcing conditions can also be detected through the Y cap of the electro-magnetic interference (EMI) filter. The detection circuit uses a rectifier circuit to rectify the detected arcing signal detected via the ring core or transformers to the control signal. When arcing occurs, the magnitude of the control signal increases, which causes the control circuit to regulate the frequency of the inverter. When the ballast operating frequency increases, the high frequency bus voltage is driven lower so that the arcing condition is eliminated.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. It is noted that the invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.
The accompanying drawings, which are incorporated herein and form part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the relevant art(s) to make and use the invention.
While the present invention is described herein with illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those skilled in the art with access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the invention would be of significant utility.
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The second AC current loop includes an input terminal J2, one EMI filter TX1, the rectifier bridge diode D3, resonant inductor L1, output capacitor C4 or C5, lamp load 150 or 155, DC blocking capacitor C6, rectifier diode D4, the capacitor Cy2 and ground terminal J3.
The resonant inverter 140 as described in more detail below generates a high frequency bus 220. First and second lamp loads 150, 155, are coupled to the high frequency bus 220 via first and second, ballasting capacitors C4, C5. Thus, if one lamp is removed, the others continue to operate. It is contemplated that any number of lamps (and corresponding ballasting capacitors) can be connected to the high frequency bus 220. Therefore, for each lamp load 150, 155, . . . Nth can be coupled to the high frequency bus 220 via an associated ballasting capacitor C4, C5, . . . CN. Power to each lamp load 150, 155, . . . Nth is supplied via connection to capacitor C6 and ground.
The Resonant Inverter 140 includes analogous upper and lower or first and second switches Q1 and Q2, for example, two n-channel metal oxide semiconductor field effect transistor (MOSFET) devices (as shown), serially connected between inputs J1 or J2 and ground, to excite the inverter 140. Two P-channel MOSFETs may also be configured. The high frequency bus 220 is generated across the resonant inverter 140 and includes a resonant inductor L1 and an equivalent resonant capacitance which includes the equivalence of first, second and third capacitors C1, C2, C3, and ballasting capacitors C4, C5, . . . CN, which also prevent DC current from flowing through the lamp loads 150, 155, . . . Nth. The ballasting capacitors C4, C5, . . . CN are primarily used as ballasting capacitors.
The switches Q1 and Q2 cooperate to provide a square wave at a common or first node N3 to excite the resonant inverter 140 across the high frequency bus 220. A control signal in connection with the switches Qi and Q2 are connected at control nodes N1 and N2.
Further in
The detection circuit 130 is configured such that as the input AC current flows through the ring core TX2, the input AC current spikes on the primary side P1 of the ring core during an arcing condition. This allows the acing condition to be detected as the input AC current flows through the first current loop J1-J3 or the second current loop J2-J3. This input AC current spike results in a corresponding DC voltage spike across the control signal on the secondary side S1 of the ring core as explained below. When the DC voltage across the control signal exceeds a preset threshold, indicating the presence of an arcing condition, the rectifier circuit 170 rectifies the control signal such that the arching condition can be extinguished by the control circuitry 160. The control circuit 160 is able to extinguish the arcing condition by generating a command signal to control the supply of the ballast output power to the lamp loads 150, 155 during the arc condition.
The detection circuit 130 can sense an arcing signal at Cy1 and Cy2 or J3 or at any point along the current loops. However, the arcing signal (the current spike as shown in
The ballast arc elimination circuit 200 is able to sense an arcing signal at Cy1 and Cy2, or J3 by employing a ring core TX2 (or transformer). The ring core TX2 is inserted between the ground line J3 and capacitors Cy1 and Cy2. The arc detection circuit 130 works in conjunction with the rectifier circuit 170 to rectifier the arcing DC voltage across the DC control signal. A DC control signal flows through the secondary coil S1 of ring core TX2 for regulating the lamp load 155. The DC control signal typically maintains a steady voltage, for example 10 volts.
When an arcing condition occurs, there is a current spike within the input AC current flowing through the primary side P1 of the ring core TX2. Based on the turn ratio of the ring core, a proportional current spike will also flow through the secondary side S1 of the ring core, which is connected to the rectifier circuitry 170 and the control circuitry 160. This proportional current spike will cause a proportional DC voltage spike within the control signal on the secondary side of the ring core S1. The control signal containing the DC voltage spike is rectified within the rectifier circuitry.
In an exemplary embodiment, the rectifier circuitry 170 is comprised of capacitors D7 and C7. When arcing occurs, the magnitude of the DC voltage across the control signal will increase. Since this control signal is also connected to the control circuit 160, there is some certain steady-state value, for example, 10 V, which the control signal normally maintains. When the magnitude of the DC voltage across the control signal increases to a value greater than the exemplary steady-state, for example, 20 V; the control circuit will regulate the frequency of the resonant inverter in order to eliminate the arching condition.
Further in
When an arcing condition occurs, an arcing input AC current spike flows through the primary coil P1 of the ring core transformer TX2, resulting in a DC voltage Vs spike flowing through the secondary core S1. This increased instantaneous DC voltage spike Vs, causes the control signal to then regulate the inverter frequency to a higher level, for example, from an exemplary 70 kHz to an exemplary 90 kHz. When the inverter frequency is driven higher, this results in a lower voltage across the HFB and load, which will extinguish the arcing condition. This process can also eliminate the need to recycle the input AC current as the arcing condition is extinguished. This is in contrast to pervious techniques that required the shut down of the inverter.
When the arcing condition is extinguished, there is no current spike flowing through ring core TX2, and the control signal then goes back to its steady state voltage, in this example, 10 V. The inverter frequency also goes back to normal condition, which is about 70 KHz, so the ballast works normally again, without the need to recycle the input AC current.
Similarly,
The present invention has been described above with the aid of functional building layers illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional layers have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.
It is to be appreciated that the Detailed Description section, and not the Summary and Abstract sections, is intended to be used to interpret the claims. The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present invention as contemplated by the inventor(s), and thus, are not intended to limit the present invention and the appended claims in any way.
