Patent Application
20140085756
1. Technical Field
The present disclosure relates to an electronic device with a protection circuit.
2. Description of Related Art
Electronic devices connected with an adapter, such as computers or fridges, include a protection chip. The protection chip is used for preventing elements in the electronic device from being damaged by a surge current generated when the adapter connects with the electronic device. The protection chip is an integrated circuit, which is usually a complicated circuit with a plurality of electronic components. However, a new chip is needed when one of internal electronic components in the chip is damaged.
Therefore, there is room for improvement in the art.
Many aspects of the embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout two views.
The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at “least one.”
The protection circuit 100 includes an interface unit 10, a first detection unit 20, a first switching unit 30, a control unit 40, a second switching unit 50, and a second detection unit 60.
The interface unit 10 connects to the load 300. In the embodiment, the interface unit 10 plugs into the load 300.
The first detection unit 20 connects between the power supply 200 and the interface unit 10. The first detection unit 20 detects whether the interface unit 10 connects with the load 300. The first detection unit 20 generates a detection signal when the load 300 is inserted into the interface unit 10, and stops generating the detection signal when the load 300 is extracted from the interface unit 10.
The first switching unit 30 connects between the power supply 200 and the control unit 40. The first switching unit 30 turns on to establish a connection between the power supply 200 and the control unit 40 in response to the detection signal, and turns off to cut off the connection between the power supply 200 and the control unit 40 when not receiving the detection signal.
The control unit 40 connects between the first switching unit 30 and the second switching unit 50. The control unit 40 is powered by the working voltage of the power supply 200 when the first switching unit 30 turns on, and generates a pulse width modulation (PWM) signal with a variable duty cycle. The PWM signal includes a first signal and a second signal. In the embodiment, the first signal is a logic high level voltage signal, and the second signal is a logic low level voltage signal.
The second switching unit 50 connects between the power supply 200 and the interface unit 10, and switches between a turned-on state and a turned-off state based on the PWM signal. In the embodiment, the second switching unit 50 turns on based on the first signal, and turns off based on the second signal.
The second detection unit 60 connects between the control unit 40 and the second switching unit 50. The second detection unit 60 detects and outputs the voltage of the second switching unit 50.
The control unit 40 further determines whether the detected voltage is equal to a predetermined voltage. If the detected voltage is equal to the predetermined voltage, the control unit 40 generates a first controlling signal for controlling the second switching unit 50 switch to the turned-on state and remaining in the turned-on state. The predetermined voltage is lower than the working voltage. In the embodiment, the predetermined voltage is 2.5V; the control unit 40 may receives a plurality of voltages in a predetermined time period based on the PWM signal, such as a second, and calculates an average voltage of the received voltages in the predetermined time. The predetermined time can be set to be one second, or two seconds or another time interval by users.
If the detected voltage is lower than the predetermined voltage, the control unit 40 adjusts the duty cycle of the PWM signal based on the detected voltage. The control unit 40 further includes a plurality of threshold voltages which are different from each other and a plurality of predetermined duty cycles which are corresponding to the threshold voltages in a one-to-one relationship. The control unit 40 further compares the detected voltage with the threshold voltages, and generates a corresponding predetermined duty cycle when the detected voltage is equal to one of the threshold voltages. The duty cycle of the PWM signal is increased gradually for increasing the time interval of the first signal, and the voltage of the second switching unit 50 is also increased gradually. In the embodiment, the threshold voltages include 0V, 0.25V, 0.75V, 1V, 1.25V, 1.5V, 1.75V, 2V, 2.25V, and 2.5V. The predetermined duty cycles include 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, and 100%.
Further, when the second switching unit 50 is in the turned-on state and the load 300 is in an abnormal state, the voltage of the second switching unit 50 becomes lower than the predetermined voltage, and the control unit 40 generates a second controlling signal for controlling the second switching unit 50 to be in the turned-off state.
Referring to
The first detection unit 20 includes a first resistor R1 and a second resistor R2. The first resistor R1 and a second resistor R2 connect between the power supply 200 and the fourth socket 4 in series.
The first switching unit 30 includes a first bipolar junction transistor Q1, a limiting resistor R3, and a capacitor C. A base of the first bipolar junction transistor Q1 is connected between the first resistor R1 and the second resistor R2. An emitter of the first bipolar junction transistor Q1 is connected to the power supply 200 through the limiting resistor R3. A collector of the first bipolar junction transistor Q1 is connected to the control unit 40. An anode of the capacitor C is connected to the collector of the first bipolar junction transistor Q1. A cathode of the capacitor C is grounded. In the embodiment, the first bipolar junction transistor Q1 is a pnp type bipolar junction transistor; and the capacitor C is a transient capacitor.
The control unit 40 includes a detection pin 42 and an output pin 44. The output pin 44 outputs the PWM signal.
The second switching unit includes a second bipolar junction transistor Q2, a metal oxide semiconductor field effect transistor (MOSFET) Q3, a first protection resistor R4, a second protection resistor R5, a third resistor R6, and a fourth resistor R7. A base of the second bipolar junction transistor Q2 is connected to the output pin 44 through the first protection resistor R4. An emitter of the second bipolar junction transistor Q2 is grounded. A collector of the bipolar junction transistor Q2 is connected to a gate of the MOSFET Q3 through the third resistor R6. Opposite terminals of the second protection resistor R5 are respectively connected to the base and the emitter of the second bipolar junction transistor Q2. A source of the MOSFET Q3 is connected to the power supply 200. A drain of the MOSFET Q3 is connected to the second socket 2. Opposite terminals of the fourth resistor R7 are respectively connected to the gate and the source of the MOSFET Q3. In the embodiment, the second bipolar junction transistor Q2 is an npn type bipolar junction transistor; the MOSFET Q3 is p-channel enhancement type MOSFET.
The second detection unit 60 includes a first pull-up resistor R8, a second pull-up resistor R9, and a fifth resistor R10. A terminal of the first pull-up resistor R8 is connected between the drain of the MOSFET Q3 and the second socket 2. An opposite terminal of the first pull-up resistor R8 is grounded through the second pull-up resistor R9. A terminal of the fifth resistor R10 is connected between the first pull-up resistor R8 and the second pull-up resistor R9. An opposite terminal of the fifth resistor R10 is connected to the detection pin 42.
The load 300 includes a first plug 11, a second plug 12, a third plug 13, and a fourth plug 14. The first plug 11 is connected to the second plug 12, and the third plug 13 is connected to the fourth plug 14.
The principle of the protection circuit 300 is described, when the interface unit 10 plugs into the load 300, the voltage difference between the base and the emitter of the first transistor Q1 is more than 0.7V, the first transistor Q1 turns on. The control unit 40 is powered on by the power supply 200. Because the MOSFET Q3 turns off, the voltage of the detection pin 42 is 0V, and the duty cycle of the PWM signal output by the output pin 44 is 5%. The second transistor Q2 and the MOSFET Q3 orderly switch between the turned-on state and the turned-off state based on the PWM signal with a 5% duty cycle. The voltage of the detection pin 42 is increased gradually and the duty cycle of the PWM signal is increased gradually. When the voltage of the detection pin 42 is 2.5V, the duty cycle of the PWM signal output by the output pin 44 is 100%, and the second transistor Q2 and the MOSFET Q3 simultaneously be in a turned-on state. As a result, the impact to the load 300 based on the surge current from the power supply 200 is reduced.
The protection circuit 200 switches between the turned-on state and the turned-off state when being plugged with the load 300. Therefore, the impact to the load 300 from the surge current generated by the power supply 200 is reduced.
It is to be understood, however, that even though information and advantages of the present embodiments have been set forth in the foregoing description, together with details of the structures and functions of the present embodiments, the disclosure is illustrative only; and changes may be made in detail, especially in the matters of shape, size, and arrangement of parts within the principles of the present embodiments to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2012103598728 | Sep 2012 | CN | national |
