Patent Grant
11900856
This patent application is a National Stage Entry of PCT/CN2021/110791 filed on Aug. 5, 2021, which claims the benefit and priority of Chinese Patent Application No. 202010961074.7 filed on Sep. 14, 2020, the disclosures of which are incorporated by reference herein in their entirety as part of the present application.
Embodiments of the present disclosure relate to a field of displaying technology, and particularly, relate to a protection circuit for a display device, a display device thereof, and a method for protecting a display device using a protection circuit.
With development of displaying technology, a display panel is developed towards a direction of high integration and low cost. At present, medium and large-sized display panels basically adopt a Gate Driver on Array (GOA) architecture. That is, a row scan driving circuit is integrated inside the display panel using the same manufacturing process as that of TFT.
Embodiments of the present disclosure provide a protection circuit for a display device, a display device thereof, and a method for protecting a display device using a protection circuit.
In an aspect of the present disclosure, a protection circuit for a display device is provided. The display device includes a gate driving circuit, a level shift circuit, and a power management circuit. The level shift circuit is configured to provide an input signal to a signal input terminal of the gate driving circuit. The power management circuit is configured to provide power to the gate driving circuit. The protection circuit is configured to provide a power control signal to the power management circuit based on a current at the signal input terminal of the gate driving circuit, so that the power management circuit stops providing the power to the gate driving circuit.
In an embodiment of the present disclosure, the protection circuit includes a control circuit, a current detection circuit, a comparison circuit, a current detection terminal and a control signal output terminal. The current detection terminal is configured to receive the current at the signal input terminal of the gate driving circuit. The control signal output terminal is configured to provide the power control signal to the power management circuit. The control circuit is coupled to the current detection circuit and the comparison circuit, and configured to send a first control signal to the current detection circuit to control an operation of the current detection circuit and send a second control signal to the comparison circuit to control an operation of the comparison circuit. The current detection circuit is coupled to the current detection terminal and the comparison circuit, and configured to detect the current at the signal input terminal of the gate driving circuit under a control of the control circuit, and send the detected current to the comparison circuit. The comparison circuit is coupled to the control signal output terminal, and configured to compare the current to a first threshold under a control of the control circuit, and to generate the power control signal at the control signal output terminal based on a comparison result.
In an embodiment of the present disclosure, generating the power control signal based on the comparison result includes: generating the power control signal at the control signal output terminal when the current is greater than the first threshold.
In an embodiment of the present disclosure, the control circuit is further configured to receive and store control parameters.
In an embodiment of the present disclosure, the control parameters include the first threshold and a detection time. The detection time is a time interval between a transition edge of a voltage signal at the signal input terminal to be detected from the gate driving circuit and a timing when the current is detected.
In an embodiment of the present disclosure, the control parameters further include a second threshold. The second threshold is a number of times N of continuous detections of the current based on the detection time, where N is an integer greater than 1, and the current detected each time is greater than the first threshold.
In an embodiment of the present disclosure, generating the power control signal based on the comparison result includes: generating the power control signal at the control signal output terminal when a plurality of detections are continuously performed and the number of detections is equal to the second threshold.
In an embodiment of the present disclosure, the signal input terminal of the gate driving circuit includes a clock signal input terminal for receiving clock signals from the level shift circuit.
In an embodiment of the present disclosure, the detection time is in a range of 2-16 μs. The first threshold is in a range of 30-200 mA. The second threshold is 4, 8, 16 or 32.
In an embodiment of the present disclosure, the detection time is 6 μs. The first threshold is 50 mA. The second threshold is 8.
In an embodiment of the present disclosure, the protection circuit and the level shift circuit or the power management circuit are integrated into a same integrated circuit.
In an embodiment of the present disclosure, the power management circuit is further configured to provide power to the level shift circuit.
In another aspect of the present disclosure, a display device including the protection circuit as described above is provided. The display device further includes a display substrate. The display substrate includes a display region for displaying and a peripheral region surrounding the display region. The gate driving circuit is located in the peripheral region.
In an embodiment of the present disclosure, the gate driving circuit includes clock signal lines in the peripheral region. The level shift circuit provides clock signals to the gate driving circuit through the clock signal lines. The current detection terminal of the protection circuit is coupled to the clock signal lines.
In yet another aspect of the present disclosure, a method for protecting a display device using the protection circuit as described above is provided. The method includes: in response to the detected current at the signal input terminal of the gate driving circuit, the protection circuit generates the power control signal; and in response to the power control signal, the power management circuit stops providing power to the gate driving circuit.
Further aspects and areas of applicability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented individually or in combination with one or more other aspects. It should further be understood that the description and specific examples herein are intended for purposes of illustration only and are not intended to limit the scope of the present application.
The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present disclosure.
Corresponding reference numerals indicate corresponding parts or features throughout the several diagrams of the drawings.
Firstly, it should be noted that, as used herein and in the appended claims, the singular form of a word includes the plural, and vice versa, unless the context clearly dictates otherwise. Thus, the references “a”, “an”, and “the” are generally inclusive of the plurals of the respective terms. Similarly, the words “comprise”, “comprises”, and “comprising” are to be interpreted inclusively rather than exclusively. Likewise, the terms “include”, “including” and “or” should all be construed to be inclusive, unless such a construction is clearly prohibited from the context. The term “example” used herein, particularly when followed by a listing of terms, is merely exemplary and illustrative and should not be deemed to be exclusive or comprehensive.
Additionally, further to be noted, when the elements and the embodiments thereof of the present application are introduced, the articles “a/an”, “one”, “the” and “said” are intended to represent the existence of one or more elements. Unless otherwise specified, “a plurality of” means two or more. The expressions “comprise”, “include”, “contain” and “have” are intended as inclusive and mean that there may be other elements besides those listed. The terms such as “first” and “second” are used herein only for purposes of description and are not intended to indicate or imply relative importance and the order of formation.
Next, in the drawings, the thickness and area of each layer are exaggerated for clarity. It should be understood that when a layer, a region, or a component is referred to as being “on” another part, it is meant that it is directly on the another part, or there may be other components in between. In contrast, when a certain component is referred to as being “directly” on another component, it is meant that no other component lies in between.
The flow diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
Exemplary embodiments will now be described more fully with reference to the accompanying drawings.
During a process for manufacturing a display device, there are certain fluctuations for factors such as equipments, process environment, and raw materials. When such fluctuations exceed process specifications, process defects will occur. Specifically, when manufacturing devices, process defects may cause wirings to be short-circuited, resulting in a short circuit; or there are more dust particles between wirings, thereby causing overlap between adjacent wirings and thus resulting in a short-circuit.
As described above, when the short circuit occurs in the signal line, both the current and the temperature at the short-circuit location increase significantly, thereby adversely affecting the operation of the gate driving circuit, and if the operation state of the gate driving circuit is continuously maintained under the short-circuit condition, it may lead to an irreversible damage to the device. In particular, for a gate driving circuit having a GOA configuration, if the short-circuit protection mechanism is lacking, the entire display substrate having the gate driving circuit will be scrapped.
The present disclosure provides a protection circuit for a display device that can stop providing power to a gate driving circuit when a signal line in the gate driving circuit of the display device is short-circuited, thereby reducing adverse effects caused by the short circuit, and thus effectively protect the display device.
In an exemplary embodiment of the present disclosure, the level shift circuit 200 may be configured to provide an input signal to a signal input terminal A of the gate driving circuit 20. As an example, the signal input terminal A of the gate driving circuit 20 may include a clock signal input terminal for receiving the clock signals from the level shift circuit 200. For example, the level shift circuit 200 may be configured to provide a clock signal CLK to the signal input terminal A of the gate driving circuit 20 through a signal output terminal B. In addition, the level shift circuit 200 may further be configured to provide a frame start signal STV and a noise reduction signal pair VDDO/VDDE for the GOA unit 210 to corresponding signal input terminals of the gate driving circuit 20 through other signal output terminals.
In an exemplary embodiment of the present disclosure, the power management circuit 300 may be configured to provide power PS1 to the gate driving circuit 20. In addition, the power management circuit 300 may further be configured to provide power PS2 to the level shift circuit 200. For example, the power management circuit 300 may provide the power PS1, PS2 to the gate driving circuit 20 and the level shift circuit 200 through output terminals C and D, respectively. In addition, the power management circuit 300 may further be configured to provide an analog voltage signal AVDD, a digital voltage signal DVDD, a common electrode voltage signal Vcom, and a grayscale reference signal GMA to the display device 1.
In an exemplary embodiment of the present disclosure, the protection circuit 400 may be configured to provide a power control signal SC to the power management circuit 300 based on a current I at the signal input terminal A of the gate driving circuit 20, so that the power management circuit 300 stops providing the power PS1 to the gate driving circuit 20. Therefore, when a short circuit occurs in the gate driving circuit 20, the protection circuit 400 can trigger circuit protection in time, so as to protect the gate driving circuit 20 and avoid a damage to the device.
In an exemplary embodiment of the present disclosure, the protection circuit 400 may include a control circuit 410, a current detection circuit 420, a comparison circuit 430, a current detection terminal E, and a control signal output terminal F.
In an exemplary embodiment of the present disclosure, the current detection terminal E may be configured to receive the current I at the signal input terminal A of the gate driving circuit 20.
In an exemplary embodiment of the present disclosure, the control signal output terminal F may be configured to provide a power control signal SC to the power management circuit 300.
In an exemplary embodiment of the present disclosure, the control circuit 410 may be coupled to the current detection circuit 420 and the comparison circuit 430, and may be configured to send a first control signal C1 to the current detection circuit 420 to control an operation of the current detection circuit 420 and send a second control signal C2 to the comparison circuit 430 to control an operation of the comparison circuit 430.
In an exemplary embodiment of the present disclosure, the current detection circuit 420 may be coupled to the current detection terminal E and the comparison circuit 430, and may be configured to detect the current I at the signal input terminal A of the gate driving circuit 20 under a control of the control circuit 410 (e.g., under the control of the first control signal C1), and send the detected current I to the comparison circuit 430.
In an exemplary embodiment of the present disclosure, the comparison circuit 430 may be coupled to the control signal output terminal F, and may be configured to compare the current I to a first threshold 10 under a control of the control circuit 530 (e.g., under the control of the second control signal C2) and generate the power control signal SC at the control signal output terminal F based on a comparison result.
In an exemplary embodiment of the present disclosure, the protection circuit 400 may be integrated into a same integrated circuit with the level shift circuit 200 and the power management circuit 300. For example, both of them may be formed in the same integrated circuit (IC). As an example, referring to
Further, in an exemplary embodiment of the present disclosure, the level shift circuit 200 may provide clock signals to the gate driving circuit through clock signal lines. Specifically, as described above, referring to
In an exemplary embodiment of the present disclosure, generating the power control signal SC based on the comparison result may include: generating the power control signal SC at the control signal output terminal F when the current I is greater than the first threshold 10.
In an exemplary embodiment of the present disclosure, the control circuit 410 may further be configured to receive and store control parameters.
As an example, the control parameters may include the first threshold 10 and a detection time t0. Specifically, the first threshold 10 may be a current threshold. The detection time t0 may be an time interval between a transition edge of a voltage signal at the signal input terminal A to be detected from the gate driving circuit 20 to a timing when the current I is detected.
Further, the control parameters may further include a second threshold N. Specifically, the second threshold N may be a number of times N of continuous detections of the current I based on the detection time t0, where N is an integer greater than 1, and the current I detected each time is greater than the first threshold 10.
In an exemplary embodiment of the present disclosure, further, generating the power control signal SC based on the comparison result may include: generating the power control signal SC at the control signal output terminal F when a plurality of detections are continuously performed and the number of detections is equal to the second threshold N. By setting the second threshold, the power control signal SC can be effectively prevented from being erroneously generated due to the current fluctuation of the gate driving circuit during the normal operation.
In an exemplary embodiment of the present disclosure, an enable signal terminal EN of the power management circuit 300 receives the power control signal SC, and stops providing the power PS1 to the gate driving circuit 20. Therefore, when the clock signal line of the signal lines 220 in the gate driving circuit 20 is short-circuited, the power PS1 provided to the gate driving circuit 20 is stopped, thereby protecting the gate driving circuit 20 and avoiding a damage to the device.
As an example, the current detection terminal E of the protection circuit 400 may be coupled to only one clock signal line, so that the location where the short circuit occurs can be located. As another example, the current detection terminal E of the protection circuit 400 may be coupled to a plurality of clock signal lines. In this case, those skilled in the art can roughly locate the location where the short circuit occurs based on known conditions such as the clock timing.
As an example, the detection time t0 may be in a range of 2-16 μs. The first threshold 10 may be in a range of 30-200 mA. The second threshold N may be 4, 8, 16 or 32.
Further, as an example, the detection time t0 may be 6 μs. The first threshold 10 may be 50 mA. The second threshold N may be 8.
As an example, the power control signal SC may include a voltage signal. For example, the voltage signal may be a low voltage signal. For example, the low voltage may be in a range of 0-0.6 V.
In an exemplary embodiment of the present disclosure, optionally, in the case where the protection circuit 400 and the power management circuit 300 are not integrated into the same integrated circuit, a signal transfer circuit may be disposed between the control signal output terminal F of the protection circuit 400 and the enable signal terminal EN of the power management circuit 300.
In an exemplary embodiment of the present disclosure, the signal transfer circuit 60 may be configured to perform noise reduction and filtering on the power control signal SC output from the control signal output terminal F. The signal transfer circuit 60 may include a resistor R and a capacitor C. As an example, the resistor R may be a zero-ohm resistor. It should be noted that,
As shown in
In an exemplary embodiment of the present disclosure, the first clock signal terminals in adjacent two stage shift register units are connected to different clock signal lines. For example, the first clock signal terminals CLK1 of SR1 and SR2 shown in
Embodiments of the present disclosure further provide a display device including the protection circuit as described above. The display device may further include a display substrate. The display substrate may include a display region for displaying and a peripheral region surrounding the display region. The gate driving circuit is located in the peripheral region.
In an exemplary embodiment of the present disclosure, the display device may further include clock signal lines in the peripheral region. The level shift circuit may provide clock signals to the gate driving circuit through the clock signal lines. The current detection terminal of the protection circuit may be coupled to the clock signal lines.
Embodiments of the present disclosure further provide a method for protecting a display device using the protection circuit as described above. Thus, when a short circuit occurs in the signal line in the gate driving circuit of the display device, the protection mechanism is triggered to stop providing power to the gate driving circuit, thereby protecting the gate driving circuit and avoiding a damage to the device.
The protection method is described in detail below with reference to
In an exemplary embodiment of the present disclosure, step S100 may further include: S101, in response to the first control signal C1 from the control circuit 210 in the protection circuit 400, the current detection circuit 420 in the protection circuit 400 receives the current I at the signal input terminal A of the gate driving circuit 20, and send the detected current I to the comparison circuit 430 in the protection circuit 400; S102, in response to the second control signal C2 from the control circuit 210, the comparison circuit 430 receives the current I from the current detection circuit 420, compares the current I to the first threshold 10, and generates the power control signal SC at the control signal output terminal F when the current I is greater than the first threshold value 10, a plurality of detections are continuously performed, and the number of detections is equal to the second threshold N.
Here, the second threshold N may be a number of times N of continuous detections of the current I based on the detection time t0, where N is an integer greater than 1, and the current I detected each time is greater than the first threshold 10. The detection time t0 may be an time interval between a transition edge of a voltage signal at the signal input terminal A to be detected from the gate driving circuit 20 to a timing when the current I is detected.
For other descriptions about the protection circuit, reference may be made to the detailed descriptions about
The foregoing description of the embodiment has been provided for purpose of illustration and description. It is not intended to be exhaustive or to limit the application. Even if not specifically shown or described, individual elements or features of a particular embodiment are generally not limited to that particular embodiment, are interchangeable when under a suitable condition, can be used in a selected embodiment and may further be varied in many ways. Such variations are not to be regarded as a departure from the application, and all such modifications are included within the scope of the application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202010961074.7 | Sep 2020 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/110791 | 8/5/2021 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2022/052688 | 3/17/2022 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20140191935 | Morii | Jul 2014 | A1 |
| 20170263166 | Chen | Sep 2017 | A1 |
| 20170316728 | Lee et al. | Nov 2017 | A1 |
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| 20200024265 | Braunschweig | Jan 2020 | A1 |
| 20210021120 | Qiu | Jan 2021 | A1 |
| 20210272530 | Hosoya | Sep 2021 | A1 |
| 20210304694 | Qiu | Sep 2021 | A1 |
| 20220005432 | Katsuta | Jan 2022 | A1 |
| 20220068179 | Jang | Mar 2022 | A1 |
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| 105162077 | Dec 2015 | CN |
| 105304050 | Feb 2016 | CN |
| 105448260 | Mar 2016 | CN |
| 107068092 | Aug 2017 | CN |
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| Entry |
|---|
| Office action issued for Chinese Application No. 202010961074.7, dated Jan. 5, 2022, 18 pages. |
| Office action issued for Chinese Application No. 202010961074.7, dated Jun. 14, 2022, 13 pages. |
| Number | Date | Country | |
|---|---|---|---|
| 20230034489 A1 | Feb 2023 | US |
