TECHNICAL FIELD
The present application relates to amplifiers. In particular, the present application relates to protection of power amplifiers (PAs).
BACKGROUND
FIG. 1A shows a prior art radio frequency (RF) power amplifier (PA) module (100a) which can be used, for example, in a transmitter section of an RF front-end communication system, such as for example, a mobile communication system. As shown in FIG. 1A, the power amplifier module (100a) can include a number of cascaded amplifier stages (e.g., driver stage A1, final stage A2), coupled in series connection via matching networks (e.g., MN0, MN1, MN2), for amplification of an input RF signal, RFin, to generate therefrom an amplified output RF signal, RFout. Power to the amplifier stages (A1, A2) may be provided via corresponding supply voltages (Vcc1, Vcc2, which may be same or separate) referenced to a reference ground, the supply voltages coupled to the amplifier stages (A1, A2) through respective inductors (L1, L2). The amplified signal, RFout, can in turn be transmitted via, for example, an antenna that is coupled to the PA module (100a) through an antenna switch (e.g., as known in the art).
As shown in FIG. 1B, each of the amplifier stages (A1, A2) may include a respective cascode arrangement of stacked (FET) transistors, (M11, M12, . . . M1k) and (M21, M22, . . . M2k), each such cascode arrangement coupled between the respective supply voltage (Vcc1, Vcc2) and the reference ground. Furthermore, as shown in FIG. 1B, biasing of each of the transistors, (M11, M12, . . . M1k) and (M21, M22, . . . M2k), may be provided via an associated biasing circuit, BIAS1 and BIAS2, that is configured to generate gate voltages to gates of each of the stacked transistors. In particular, a (gain setting) DC biasing current (e.g., ICC1, ICC2) that flows through each of the transistor stacks, (M11, M12, . . . M1k) and (M21, M22, . . . M2k), may be predominantly based, during normal operating conditions of the PA module (100a), on a gate voltage provided to a respective input transistor (e.g., M11, M12). In other words, a gain of each of the amplifier stages (A1, A2), i.e., a ratio between RF power at a corresponding (drain of an) output transistor (e.g., M1k, M2k) and RF power at a corresponding (gate of an) input transistor (e.g., M11, M21), may be based on the respective DC biasing current (e.g., ICC1, ICC2).
Normal operating conditions of the PA module (100a) may include a high limit of the input RF power provided by the input RF signal, RFin, which in turn may define a high limit of the output RF power of the amplifier stage A1 that is provided as input to the amplifier stage A2. However, under certain conditions, whether controlled (e.g., during ruggedness test) or not (e.g., transients), the input RF power to the amplifier stage A1 may go above the high limit and/or include a DC component (e.g., an average DC component in the RF signal) that may couple to the gate of the input transistor, M11, to provide a higher gain (i.e., higher magnitude ICC1) of the amplifier stage A1. In combination, such effects may produce an input RF signal to the amplifier stage A2 that may include an amplitude that is sufficiently high to damage, or at least affect performance (e.g., hot carrier injection), of the corresponding input transistor, M21. In other words, an amplitude of the RF signal to the amplifier stage A2 may cause any one of the gate-to-source voltage, Vgs, the gate-to-drain voltage, Vgd, or the drain-to-source voltage, Vds, of the input transistor, M21, to reach sufficiently high levels to damage and/or affect performance of the transistor.
It follows that there may be a need for improved protection of an RF amplifier module against high input RF power conditions that may not be considered as normal operating conditions. Teachings according to the present disclosure provide such improved protection while maintaining an ongoing activity of the RF amplifier module.
SUMMARY
According to a first aspect of the present disclosure, a circuit is presented, comprising: a plurality of cascaded amplifier stages; and a protection circuit coupled to a supply voltage node of a first stage of the plurality of cascaded amplifier stages, the first stage operating between the supply voltage node and a reference ground, wherein the protection circuit comprises: a current limiter circuit configured to limit a high value of a supply current that flows from the supply voltage node to the reference ground through the first stage, the high value of the supply current based on a magnitude of a reference current.
According to a second aspect of the present disclosure, a method for protecting a multi stage amplifier from high input power condition is presented, the method comprising: coupling an output leg of a current limiter circuit to a supply voltage node of a first stage of the multi stage amplifier; and based on the coupling, limiting a high value of a current that flows from the supply voltage node through the first stage based on a reference current that flows through an input leg of the current limiter.
BRIEF DESCRIPTION OF DRAWINGS
The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present disclosure and, together with the description of example embodiments, serve to explain the principles and implementations of the disclosure.
FIG. 1A shows a prior art RF power amplifier (PA) module including a plurality of cascaded amplifier stages.
FIG. 1B shows an example implementation of the cascaded amplifier stages of the PA module.
FIG. 2A shows a configuration according to an embodiment of the present disclosure of a RF power amplifier (PA) module with a protection circuit.
FIG. 2B and FIG. 2C show graphs representative of performance advantages provided by the protection circuit of FIG. 2A.
FIG. 3A shows a simplified schematic of a current limiter circuit according to an embodiment of the present disclosure that may be used in the protection circuit of FIG. 2A.
FIG. 3B and FIG. 3C show graphs representative of performance advantages provided by the current limiter circuit of FIG. 3A.
FIG. 4A, FIG. 4B and FIG. 4C show simplified schematics of other current limiter circuits according to further embodiments of the present disclosure that may be used in the protection circuit of FIG. 2A.
FIG. 5A and FIG. 5B show graphs representative of possible performance disadvantages that may be provided by the current limiter circuit according to the present disclosure.
FIG. 5C shows a simplified schematic of a biasing circuit according to an example embodiment of the present disclosure that may be used to overcome the possible performance disadvantages represented in FIG. 5A and FIG. 5B.
FIG. 6A shows a simplified schematic of a current limiter circuit with output voltage clamping according to an example embodiment of the present disclosure.
FIG. 6B and FIG. 6C show graphs representative of performance advantages provided by the current limiter circuit with output voltage clamping of FIG. 6A.
FIG. 7 shows a simplified schematic of a current limiter circuit with pre-charge of an output voltage according to an example embodiment of the present disclosure.
FIG. 8A shows a configuration according to another embodiment of the present disclosure of a RF power amplifier (PA) module with a protection circuit that is coupled to a final stage.
FIG. 8B shows a configuration according to yet another embodiment of the present disclosure of a RF power amplifier (PA) module with a protection circuit that is coupled to any one of a plurality of stages.
FIG. 8C shows a configuration according to yet another embodiment of the present disclosure of a RF power amplifier (PA) module with a protection circuit that is shared amongst a plurality of stages.
FIG. 9 shows a configuration according to yet another embodiment of the present disclosure of a protection circuit that is shared amongst a plurality of RF power amplifier (PA) modules.
FIG. 10 shows a simplified schematic of a current limiter circuit with an embedded RF filter according to an example embodiment of the present disclosure.
FIG. 11 shows a configuration according to an embodiment of the present disclosure of a RF power amplifier (PA) module with a protection circuit whose operation may be controlled based on detected parameter values.
FIG. 12 shows a configuration according to an embodiment of the present disclosure of a RF power amplifier (PA) module with a protection circuit, the RF PA module including a bipolar transistor.
FIG. 13 is a process chart showing various steps of a method according to an embodiment of the present disclosure.
Like reference numbers and designations in the various drawings indicate like elements.
DETAILED DESCRIPTION
Throughout the present disclosure, embodiments and variations are described for the purpose of illustrating uses and implementations of inventive concepts of various embodiments. The illustrative description should be understood as presenting examples of the inventive concept, rather than as limiting the scope of the concept as disclosed herein.
FIG. 2A shows a configuration according to an embodiment of the present disclosure comprising an RF power amplifier (PA) module (200a) that includes a protection circuit (220) that is coupled to a first (e.g., driver) stage A1 of the PA module (200a). According to an embodiment in accordance with the present disclosure, the protection circuit (220) may include a current limiter (circuit) that is configured to limit a magnitude of a current supplied to the first stage A1. In other words, the current limiter of the protection circuit (220) may limit a high value of the DC biasing/supply current ICC1, and therefore limit a gain of the first stage, A1. By limiting the gain of the first stage A1, an input power to the second (e.g., final) stage A2 may be limited to values that may not damage or otherwise negatively affect performance of the second stage, A2, including of the input transistor (e.g., M21) of the second stage, A2.
The protection circuit (220) according to the present teachings may be designed to limit the current supplied to a stage (e.g., A1) only for values of an input RF power to the stage (e.g., RFin) that are beyond/greater than values expected under normal operating conditions of the PA module (200a). According to an embodiment in accordance with the present disclosure, limiting of the current supplied to the stage (e.g., A1) may not halt operation of such stage, and therefore may allow maintaining of an ongoing activity of the PA module (200a).
FIG. 2B and FIG. 2C show graphs representative of performance advantages provided to the PA module (200a) by the protection circuit of FIG. 2A when compared to the (unprotected) prior art PA module (e.g., 100a of FIG. 1A). In such graphs, normal operating conditions of the PA modules (200a, 100a) are represented by an input power, Pin, to the first stage (e.g., A1 of FIGS. 1A, 2A) in a range of values to the left of (i.e., smaller than) a power limit line, NL (shown at an example input power limit value of −5 dBm). As shown in FIG. 2B, during normal operating conditions, the supply current (e.g., ICC1, labeled as CL in the graph) to the first stage, A1, of the (protected) PA module (e.g., 200a of FIG. 2A) is substantially same as the supply current (e.g., ICC1 labeled as CV in the graph) to the first stage, A1, of the (unprotected) prior art PA module (e.g., 100a of FIG. 1A). However, for values of the input power, Pin, that are greater than the input power limit (e.g., right of the power limit line NL), the supply current (e.g., ICC1, labeled as CL in the graph) to the (protected) PA module (e.g., 200a of FIG. 2A) gradually flattens when a current limit is reached (e.g., where the two graphs separate), whereas the supply current (e.g., ICC1, labeled as CV in the graph) to the prior art (unprotected) PA module (e.g., 100a of FIG. 1A) constantly increases (with no upper current limit). Accordingly, as shown in the graphs of FIG. 2C, the output power, Pout, of the first stage A1, for the protected (CL) and unprotected (CV) configurations may follow same trend as the supply currents. In particular, as shown in FIG. 2C, and as a consequence of the current limiting, for values of the input power, Pin, to the first stage (e.g., A1 of FIGS. 1A, 2A) that are greater than the input power limit (e.g., right of the power limit line NL), the output power, Pout, (labeled as CL in the graph) of the first stage A1 of the (protected) PA module (e.g., 200a of FIG. 2A) stops increasing (e.g., gradually decreases when the current limit is reached), whereas the output power, Pout, (labeled as CV in the graph) of the first stage A1 of the prior art (unprotected) PA module (e.g., 100a of FIG. 1A) constantly increases (with no upper power limit). More details on such graphs can be found later in the present disclosure (e.g., with reference to FIG. 3A).
FIG. 3A shows a simplified schematic of a current limiter circuit (222, 225) according to an embodiment in accordance with the present disclosure that may be included in the protection circuit (220) described above with reference to FIG. 2A. In the particular case shown in FIG. 3A, stages (A1, A2) of a PA module (300a) are shown to include respective cascode arrangement of stacked (FET) transistors, (M11, M12, . . . M1k) and (M21, M22, . . . M2k), as described above with reference to FIG. 1B. According to an embodiment in accordance with the present disclosure, the current limiter (222, 225) may include a reference current source (222) coupled to a current mirror (225). The reference current source (222) may generate a reference current, Iref, that may be used by an input leg (e.g., PMOS FET transistor MIN) of the current mirror (225), to generate therefrom a current conducted through the output leg (e.g., PMOS FET transistor MOUT) that may be used as the biasing/supply current, ICC1, to the first stage, A1. As shown in FIG. 3A, the transistors (MIN, MOUT) of the current mirror (225) may be coupled to one another through their respective gates, and coupled to a supply voltage, Vdd, through their respective sources. Drain of the input transistor, MIN, of the current mirror (225) may be coupled to the reference current source (222), and drain of the output transistor, MOUT, of the current mirror (225) may be coupled to the first stage, A1, through the inductor, L1. In particular, as shown in FIG. 3A, the drain of the output transistor, MOUT, of the current mirror (225) may be coupled to the drain of the output (NMOS FET) transistor, M1k, of the cascode arrangement of stacked (FET) transistors, (M11, M12, . . . M1k). A bypass capacitor, C1, may be coupled at an output of the protection circuit (220), or in other words, at the supply voltage node, VCC1, so to reduce coupling of RF frequency components to the protection circuit (220). In other words, the bypass capacitor, C1, in combination with the inductor, L1, may form a filter that is configured to reduce such coupling of the RF frequency components to the protection circuit (220).
With continued reference to FIG. 3A, in some embodiments, the current limiter (222, 225) may limit a high value (magnitude) of the supply current, ICC1, based on a mirrored value of the reference current, Iref. In some embodiments, such mirrored value may be ratiometrically related to the reference current, Iref, based on, for example, ratio of respective sizes of the transistors (MIN, MOUT) of the current mirror (225). For a nonlimiting example case where the ratio of the sizes of the transistors (MIN, MOUT) is one (same size transistors), then the mirrored value of the reference current, Iref, that determines the high value of the supply current, ICC1, may be equal to the value of the reference current, Iref.
When the current limiter (222, 225) is coupled to the first stage, A1, as shown in FIG. 3A, the supply current, ICC1, output by the current limiter (222, 225) may follow a demand current based on a biasing of the input transistor, M11, of the first stage, A1, up to a limit that is determined by the mirrored value of the reference current, Iref. During a current limiting condition, or in other words when the demand current is greater than the mirrored value of the reference current, Iref, a voltage at the supply voltage (node), VCC1, may decrease in order to limit the current through the first stage, A1, which in turn may increase, to some extent, the current conducted through the output leg (e.g., transistor MOUT sees a different bias condition) of the current limiter (222, 225) beyond the mirrored value as shown in the graph (CL) of FIG. 2B. At the same time, such decrease of the voltage at the supply voltage, VCC1, during the current limiting condition, may decrease, to some extent, the power output by the first stage as shown in the graph (CL) of FIG. 2C.
With continued reference to FIG. 3A, in some embodiments flexibility and advantages provided by the current limiter (222, 225), include, for example: protection, via limiting of current to at least one stage of a PA module (e.g., 300a of FIG. 3A) for high input power conditions, without halting operation of the (protected) PA module; no delay in protection for the high input power conditions since no detection schemes (e.g., current or power sensor) are used, rather the limiting of the current is a (natural) response of a supply current circuit to the at least one stage; absence of any oscillation risk that may be contributed by various feedback methods (e.g., RF power detection and feedback to limit a supply current); tunability and/or selectivity of a (high) value of the (limiting) current (e.g., current limit) via a tunable/selectable Iref current source/generator (e.g., 222 of FIG. 3A, and 422a/b of FIGS. 4A/4B later described), and therefore of a corresponding input power limit value (e.g., threshold) defining the high input power conditions; capability to include temperature compensation/profile for the limiting current (and therefore power) as later described with reference to FIG. 4C; capability to protect any one or more of a plurality of stages of the PA module, including of the final stage, as later described with reference to FIGS. 8A/8B/8C; capability to share a same protection circuit (e.g., current limiter) with a plurality of PA modules as later described with reference to FIG. 9; capability to further control a high value of the limiting current (e.g., value of the current limit) based on other detectable parameters such as, for example, temperature or voltage/power levels, as later described with reference to FIG. 11; and capability for use with either a MOS PA module that includes MOS devices (e.g., FIG. 3A) or a bipolar PA module that may include bipolar devices, such as GaAs (Gallium Arsenide) devices (e.g., FIG. 12 later described).
FIG. 3B and FIG. 3C show graphs representative of performance advantages provided by the current limiter circuit (222, 225) of FIG. 3A in protecting elements/transistors of the stage A2. In other words, by limiting a supply current (e.g., ICC1 of FIG. 3A) to a first stage (e.g., A1 of FIG. 3A), elements/transistors of a next/second stage (e.g., A2 of FIG. 3A) can be protected against high input RF power conditions to which a multi-stage PA module (e.g., 300a of FIG. 3A) comprising the first stage and next stage may be subjected. Advantageously, by not coupling a protection circuit (e.g., 220 of FIG. 3A) to a higher power final stage (e.g., A2 of FIG. 3A) of the multi-stage PA module, overall RF performance of such module may be maintained since a flow of a high supply current to the final stage through the protection circuit may be avoided.
As shown in the graphs of FIG. 3B and FIG. 3C, labeled as CV, (AC peak values of) the gate-to-source voltage, Vgs21, and of the drain-to-source voltage, Vds21, of the input transistor, M21, of a second/final (unprotected) stage (e.g., A2 of FIG. 1B) may steadily increase for increasing values of the input power, Pin, to a first/driver (unprotected) stage (e.g., A1 of FIG. 1B). In particular, when operating under high input RF power conditions (right side of the line NL), the voltages, Vgs21 and Vds21, of the (unprotected) second/final stage may reach values (e.g., 2 volts and higher) that may be higher than a voltage withstand capability (e.g., about 2 volts) of the input transistor, M21, thereby potentially damaging such transistor.
On the other hand, as shown in the graphs of FIG. 3B and FIG. 3C, labeled as CL, (AC peak values of) the gate-to-source voltage, Vgs21, and of the drain-to-source voltage, Vds21, of the input transistor, M21, of a second/final (protected) stage (e.g., A2 of FIG. 3A) may gradually flatten when a first/driver (protected) stage (e.g., A1 of FIG. 3A) operates under high input RF power conditions (right side of the line NL), in particular, when the supply current to the first/drive stage reaches the current limit. Because of such flattening (i.e., current/power limiting), the voltages, Vgs21 and Vds21, of the (protected) second/final stage may not reach values that may be higher than the voltage withstand capability (e.g., about 2 volts) of the input transistor, M21, thereby protecting such transistor.
FIG. 4A, FIG. 4B and FIG. 4C show simplified schematics of current limiter circuits according to further embodiments of the present disclosure that may be used in the protection circuit (220) of FIG. 2A. In particular, such figures show different example circuits (e.g., 422a, 422b, 422c) for generation of the reference current, Iref, that may be provided to the input leg (e.g., MIN) of the current mirror (225). These include, for example, the voltage to current convertor circuit (422a) of FIG. 4A which generates a reference current, Iref, based on a reference voltage, Vref, provided to a gate of a common-source (e.g., NMOS FET) transistor, Mref. Accordingly, a value of the reference current, Iref, may be controlled/tuned/changed based on a value of the reference voltage, Vref, according to the I-V characteristics of the transistor Mref.
FIG. 4B shows another example voltage to current convertor circuit (422b) that may be used for generation of the reference current, Iref. In such implementation, a voltage, Vbg, input at a non-inverting input terminal (annotated by sign+ in the FIGURE) of an operational amplifier, Op, and reproduced at the inverting input terminal (annotated by sign− in the FIGURE) of the operational amplifier, Op, is coupled to a source of a transistor, Mref. Because the source of the transistor, Mref, is coupled to the reference ground through a (shunted) resistor, Rref, then a voltage drop across the resistor, Rref, is equal to the voltage, Vbg, and therefore a current (i.e., Iref) through the transistor, Mref, is equal to the ratio of Vbg/Rref. According to an example embodiment of the present disclosure, the resistor, Rref, may optionally have a programmable, variable, or settable resistance than can be controlled/varied in steps and/or continuously. Such programmability of the resistor Rref can allow calibration of the voltage, Vbg, versus current, Iref, response provided by the circuit (422b).
Generation of the reference current, Iref, may include temperature compensation as shown in the circuit (422c) of FIG. 4C. In such implementation, the current, Iref, generated by the circuit (422c) may include a temperature profile designed to compensate for (e.g., take into account) a performance variation/sensitivity of the PA module to temperature variation, which may include for example, an increase, or a decrease, of a nominal biasing current (e.g., ICC1) for a given performance metric (e.g., for a given output power). By providing such temperature profile, the reference current, Iref, and therefore, triggering of a current limiting condition, may be adapted to the sensitivity of (a stage of) the PA module at a given temperature. In some embodiments, design techniques for implementation of such temperature profile, may include, for example, use of one or more of a proportional to absolute temperature (PTAT) profile, a complementary proportional to absolute temperature (CTAT) profile, or a zero-proportionality to absolute temperature (ZTAT) profile.
FIG. 5A and FIG. 5B show graphs representative of possible performance disadvantages that may be provided by the current limiter circuit of the protection circuit (220) described above (e.g., FIGS. 2A-4C), and FIG. 5C shows a simplified schematic of a biasing circuit (shown encircled as detail α) according to an example embodiment of the present disclosure that may be used to overcome the possible performance disadvantages shown in FIG. 5A and FIG. 5B. In particular, FIG. 5C shows a portion of the configuration described above with reference to FIG. 3A that relates to the first stage, A1, and the protection circuit (220), wherein such protection circuit (220) includes a reference current source/generator (522) that may be any of the above-described current source/generators (222, 422a/b/c) with reference to FIG. 3A and FIGS. 4A/4B/4C.
As previously noted with reference to FIG. 3A, and as shown in the graph of FIG. 5A with further reference to FIG. 5C, when the demand current by the input transistor, M11, of the first stage A1 is greater than the mirrored value of the reference current, Iref, or in other words, during a current limiting condition where the demand current is greater than the (limit) current the current limiter (522, 225) can generate/source, then a voltage at the supply voltage (node), VCC1, may decrease in order to limit the current through the first stage, A1. Such decrease of the supply voltage, VCC1, which can be seen to the right of the power limit line, NL, of FIG. 5A, can be up to several volts (DC). Considering the output (top) transistor, M1k, of the first stage A1, a corresponding drain voltage, which is DC coupled to the supply voltage, VCC1, may vary along with the supply voltage, VCC1. Accordingly, if the gate voltage, Vg1k, to the gate of the output transistor, M1k, is fixed/constant, then as shown in FIG. 5B, a gate-to-drain voltage, Vgd1k, of the output transistor, M1k, may vary along with the supply voltage, VCC1, and may reach a voltage level that may be sufficiently high to damage or otherwise affect performance of the output transistor, M1k, and therefore of the first stage, A1, and of the PA module in general. On the other hand, by letting the gate voltage, Vg1k, to the gate of the output transistor, M1k, vary along with the supply voltage, VCC1, as done by the biasing circuit shown in FIG. 5C as detail α, then the gate-to-drain voltage, Vgd1k, of the output transistor, M1k, may remain substantially fixed/constant in view of the varying of the supply voltage, VCC1. The biasing circuit shown in FIG. 5C as detail α, may include a resistor ladder comprising series-connected resistors (R1, R2, . . . , Rk) coupled between the supply voltage node), VCC1, and the reference ground to provide respective gate biasing voltages (Vg12, . . . , Vg1k) to the gates of the transistors (M12, . . . , Vg1k).
FIG. 6A shows a simplified schematic of a current limiter circuit (225, 522) with output voltage clamping according to an example embodiment of the present disclosure. As shown in FIG. 6A, according to an embodiment of the present disclosure, a clamping circuit (625) may be used to clamp/limit a low value of a voltage at an output of the current limiter circuit (225) that is coupled/connected to the supply voltage (node), VCC1. Accordingly, an extent of a decrease of a voltage at the supply voltage (node), VCC1, during a current limiting condition as described above with reference to FIGS. 5A/5C may be controlled/limited by the clamping circuit (625), and therefore, protection of the output (top) transistor, M1k, of the first stage A1, against overvoltage (voltages higher than the withstand voltage) may be provided. In other words, the clamping circuit (625) of FIG. 6A may provide a solution to a transistor overvoltage problem associated with the decreasing voltage at the supply voltage (node), VCC1, during the current limiting condition that is different from the solution provided by the biasing circuit shown in detail α of FIG. 5C. It should be noted that although both configurations of FIG. 5C and FIG. 6A may address a same problem, they may be used as separate solutions to the problem or together.
The clamping circuit (625) shown in FIG. 6A may include a (clamping, PMOS) transistor, MC, comprising: a gate that is connected to the output of the current limiter circuit (225), and therefore to the drain of the transistor MOUT, and to the node VCC1; a source that is connected to a common (gate) node, NCG, that connects the gates of the transistors (MIN, MOUT) of the current mirror (225); and a drain that is coupled to the reference ground through a load (Load). During normal operating conditions, the voltage at the node VCC1 may be high enough to establish a gate-to-source voltage of the transistor, MC, that is sufficiently low to maintain the transistor, MC, in an OFF state (e.g., non-conducting state). On the other hand, during the current limiting condition, as the voltage at the node VCC1 decreases, the gate-to-source voltage of the transistor, MC, may increase until it reaches a level that is sufficiently high to turn ON (e.g., ON state, conducting state) the transistor, MC. Turning ON of the transistor, MC, may in turn lower a voltage at the common (gate) node, NCG, to allow an increase in the current, ICC1, output by the transistor, MOUT, while maintaining the gate-to-source voltage of the transistor, MC, at a substantially fixed/constant level (e.g., about 0.6 volts). Accordingly, a (low limit) voltage at the node VCC1 may be established by the sum of the gate-to-source voltages of the transistors, MCC1 and MIN, or in other words, at about Vdd−(2*0.6) volts (assuming a gate-to-source voltage of about 0.6 volts). Other low limit (clamping) voltage values may be obtained by designing the transistors, MCC1 and MIN, to provide corresponding ON state gate-to-source voltages (i.e., threshold voltages).
FIG. 6B and FIG. 6C show graphs representative of performance advantages provided by the current limiter circuit (225, 522) with output voltage clamping of FIG. 6A. In particular, in the current limiting condition (right side of line NL), when no output voltage clamping is provided, as shown in graph, CL of FIG. 6B, the voltage at the node, VCC1, steadily/continuously decreases to reach levels that may be sufficiently low to cause, as shown in graph CL of FIG. 6C, an overvoltage condition (e.g., about 2 volts) of the gate-to-drain voltage, Vgd1k, of the output transistor, M1k. On the other hand, in the current limiting condition (right side of line NL), when output voltage clamping is provided, as shown in graph, CLP of FIG. 6B, the voltage at the node, VCC1, decreases at a slower rate compared to the graph CL of FIG. 6B, such as to reach a low/clamped level that may be sufficiently high not to cause, as shown in graph CLP of FIG. 6C, an overvoltage condition (e.g., about 2 volts) of the gate-to-drain voltage, Vgd1k, of the output transistor, M1k.
FIG. 7 shows a simplified schematic of a current limiter circuit (725, 522) with pre-charge of an output voltage according to an example embodiment of the present disclosure. As shown in FIG. 7, a (switching) pre-charge circuit (728) may be coupled to the current mirror (725) in order to pre-charge the bypass capacitor, C1, prior to operation/use (e.g., during a standby mode of operation) of the current limiter circuit (725, 522), thereby improving a turn on time of the current limiter circuit (725, 522) that may include a charging time of the bypass capacitor, C1, to a nominal operating voltage (at the node VCC1).
According to an example embodiment of the present disclosure, as shown in FIG. 7, the pre-charge circuit (728) may include a first (e.g., single-pole, single throw, SPST) switch, SW1, having respective terminals coupled/connected to the common (gate) node, NCG, and reference ground, and a second (e.g., single-pole, single throw, SPST) switch, SW2, having respective terminals coupled/connected to the common (gate) node, NCG, and drain node of the transistor, MIN, of the current mirror (725). During a pre-charge mode of operation (shown in FIG. 7, pre-charge circuit 728 activated), the first switch, SW1, may be closed and the second switch, SW2, may be open, therefore the gate of the transistor, MOUT, of the current mirror (725) may be grounded and the transistor, MOUT, may conduct a current to charge the bypass capacitor, C1, to the nominal operating voltage. At the same time, the second switch, SW2, may be open, so to remove possibility of a current leaked through the transistor, MIN, to reach the common (gate) node, NCG, and potentially impact the conducting state of the transistor, MOUT. On the other hand, when the pre-charge circuit (728) is not activated (e.g., deactivated, inactive), the first switch, SW1, may be open and the second switch, SW2, may be closed, therefore reestablishing the configuration of the current limiter circuit (725, 522) according to the current limiter circuits described above, including, for example, reestablishing connection of the drain of the transistor, MIN to the common (gate) node, NCG, and decoupling the common (gate) node, NCG, from the reference ground.
As shown in FIGS. 8A/8B/8C, the protection circuit (220) including any of the current limiter circuits described above with optional performance enhancements (e.g., FIG. 5C/6A/7), may be used/coupled to any one or more stages of a PA module to protect the PA module by limiting a current to a stage for protection of the same stage and/or protection of any next stage (not necessarily an immediate next/adjacent stage). This may include, for example, connection/coupling to: an output stage (e.g., A2) according to the configuration (800a) of FIG. 8A; a stage Ak of a plurality, p, of cascaded stages (A1, . . . , Ak, . . . , Ap) according to the configuration (800b) of FIG. 8B; or a plurality of stages (e.g., A1 and Ak) so that, as shown in the configuration (800c) of FIG. 8C, such stages (e.g., A1 and Ak) share a same protection circuit (220). It should be noted that such configurations may impose different requirements (e.g., current magnitudes, size of transistor MOUT) on the current limiting circuit, that may be based, for example, on operating power conditions/levels of the stages to which the protection circuit may be coupled.
FIG. 9 shows a configuration (900) according to yet another embodiment of the present disclosure of a protection circuit (e.g., 220 that includes a current limiter) that is shared amongst a plurality of RF power amplifier (PA) modules (PA1, PA2, . . . , PAk), each including a plurality of cascaded stages (e.g., A11, A21; A12, A22; . . . ; and A1k, A2k) and a plurality of matching networks (e.g., MN01, MN11, MN21; MN02, MN12, MN22; . . . ; and MN0k, MN1k, MN2k). In the configuration (900) shown in FIG. 9, at any given time one of the PA modules (PA1, PA2, . . . , PAk) may be coupled to an antenna (not shown) via an antenna switch (not shown) for transmission of an amplified RF signal (RFout1, RFout2, . . . , RFoutk). It should be noted that a stage (e.g., A11, A12, A1k) of each of the PA modules (PA1, PA2, . . . , PAk) to which the protection circuit (220) with current limiter is coupled/connected to, may impose different requirements (e.g., current magnitudes, size of transistor MOUT) on the current limiting circuit based on respective operating power conditions/levels. Programmability of the reference current (e.g., Iref generated by circuit 222 of FIGS. 4A/4B) of the current limiter circuit used in the protection circuit (220), and/or of a ratio of sizes of the transistors MIN and MOUT, may allow to program different current limits for each of the PA modules (PA1, PA2, . . . , PAk).
FIG. 10 shows a simplified schematic of a current limiter circuit (225, 522) with an embedded RF filter circuit (1025) according to an example embodiment of the present disclosure. The current limiter circuit (225, 522) may include a reference current source/generator (522) that may be any of the above-described current source/generators (222, 422a/b/c) with reference to FIG. 3A and FIGS. 4A/4B/4C. The RF filter circuit (1025) may include a resistor, RFL, in series connection between the gates of the transistors (MIN, MOUT) of the current mirror (225), and a capacitor, Cry having a first terminal connected to the resistor RFL, at the gate of the transistor MOUT, and a second terminal connected to the supply voltage, Vdd. The combination of the resistor, RFL, and capacitor, Cry may form a filter that may attenuate components of an RF signal coupled to the inductor L1 that may not be sufficiently attenuated by the combination of (L1, C1), including, for example, an RF envelope signal. Because such RF envelope signal may include a frequency that is sufficiently lower than a center frequency of the RF signal targeted for attenuation by the combination of (L1, C1), it may not be sufficiently attenuated by latter combination. Attenuation/removal of RF signal related frequency components, including higher frequency components via (L1, C1) and lower frequency components via (RFL CFL) may allow improved stability/performance of the current limiter circuit (225, 522).
FIG. 11 shows a configuration (1100) according to an embodiment of the present disclosure of a RF power amplifier (PA) module (e.g., comprising cascaded stages A1, . . . , Ak, . . . , Ap) with a protection circuit (220) whose operation may be controlled based on detected parameter values. As shown in FIG. 11, a detector circuit (1145) may detect values of one or more parameters and feed such values to a controller circuit (1135) that may correspondingly control operation of the protection circuit (220), including operation of the current limiter. According to an example embodiment of the present disclosure, the one or more parameters detected (e.g., sensed) by the detector may be: a temperature, such as a local temperature (e.g., at vicinity of the PA module or a stage thereof) or an ambient temperature (e.g., of room where a device containing the PA module operates); or a voltage, including, for example, a battery voltage (e.g., Vdd). Based on the detected parameter(s) value(s), the controller circuit (1135) may, for example, control/modify magnitude of the reference current (e.g., Iref of FIGS. 4A/4B), and therefore control/modify the current limit that may trigger a current limiting condition.
FIG. 12 shows a configuration (1200) according to an embodiment of the present disclosure of a RF power amplifier (PA) module with a protection circuit, the RF PA module including bipolar transistors (e.g., Tr1, Tr2). The configuration (1200) of FIG. 12 may be likened to the configuration (300a) described above with reference to FIG. 3A, with stages (A1, A2) of the PA module including respective bipolar transistors (Tr1, Tr2) instead of the cascode arrangement of stacked (MOS FET) transistors, (M11, M12, . . . M1k) and (M21, M22, . . . M2k). Accordingly, by limiting a (DC) supply current, ICC1, to a first stage, A1, the stage itself as well as a next stage, A2 may be protected against high input RF power conditions, as described with reference to FIGS. 2A-11.
FIG. 13 is a process chart (1300) showing various steps of a method for protecting a multi-stage amplifier from high input power condition. As can be seen in the process chart (1300), the method comprises: coupling an output leg of a current limiter circuit to a supply voltage node of a first stage of the multi-stage amplifier, per step (1310), and based on the coupling, limiting a high value of a current that flows from the supply voltage node through the first stage based on a reference current that flows through an input leg of the current limiter, per step (1320).
It should be noted that the various embodiments of the PA module with protection circuit with current limiting for soft shutdown according to the present disclosure may be implemented as a monolithically integrated circuit (IC) according to any fabrication technology and process known to a person skilled in the art.
Applications that may include the novel apparatus and systems of various embodiments include electronic circuitry used in high-speed computers, communication and signal processing circuitry, modems, single or multi-processor modules, single or multiple embedded processors, data switches, and application-specific modules, including multilayer, multi-chip modules. Such apparatus and systems may further be included as sub-components within a variety of electronic systems, such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., mp3 players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.) and others. Some embodiments may include a number of methods.
The term “MOSFET” technically refers to metal-oxide-semiconductors; another synonym for MOSFET is “MISFET”, for metal-insulator-semiconductor FET. However, “MOSFET” has become a common label for most types of insulated-gate FETs (“IGFETs”). Despite that, it is well known that the term “metal” in the names MOSFET and MISFET is now often a misnomer because the previously metal gate material is now often a layer of polysilicon (polycrystalline silicon). Similarly, the “oxide” in the name MOSFET can be a misnomer, as different dielectric materials are used with the aim of obtaining strong channels with smaller applied voltages. Accordingly, the term “MOSFET” as used herein is not to be read as literally limited to metal-oxide-semiconductors, but instead includes IGFETs in general.
Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice and various embodiments of the invention may be implemented in any suitable IC technology (including but not limited to MOSFET and IGFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), GaN HEMT, GaAs pHEMT, and MESFET technologies.
However, the inventive concepts described above are particularly useful with an SOI-based fabrication process (including SOS), and with fabrication processes having similar characteristics. Fabrication in CMOS on SOI or SOS enables low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (in excess of about 10 GHz, and particularly above about 20 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.
Voltage levels may be adjusted or voltage and/or logic signal polarities reversed depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functions without significantly altering the functionality of the disclosed circuits.
The examples set forth above are provided to give those of ordinary skill in the art a complete disclosure and description of how to make and use the described embodiments and are not intended to limit the scope of what the applicant considers to be the invention. Such embodiments may be, for example, used within mobile handsets for current communication systems (e.g., WCDMA, LTE, WiFi, etc.) wherein amplification of signals with frequency content of above 100 MHz and at power levels of above 50 mW may be required. The skilled person may find other suitable implementations of the presented embodiments.
Modifications of the above-described modes for carrying out the methods and systems herein disclosed that are obvious to persons of skill in the art are intended to be within the scope of the following claims. All patents and publications mentioned in the specification are indicative of the levels of skill of those skilled in the art to which the disclosure pertains. All references cited in this disclosure are incorporated by reference to the same extent as if each reference had been incorporated by reference in its entirety individually.
It is to be understood that the disclosure is not limited to particular methods or systems, which can, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in this specification and the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the content clearly dictates otherwise. The term “plurality” includes two or more referents unless the content clearly dictates otherwise. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure pertains.
A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications can be made without departing from the spirit and scope of the present disclosure. Accordingly, other embodiments are within the scope of the following claims.
Patent Application
20240162864
