The subject matter herein generally relates to a protection circuit.
A power supply unit of a computer supplies power to a device which is externally connected to the computer. The power supply is coupled to ground when the device is short-circuited.
Implementations of the present technology will now be described, by way of example only, with reference to the attached FIGURE.
The FIGURE is a circuit diagram of an embodiment of a protection circuit for a power supply unit.
It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the FIGURE to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawing is not necessarily to scale and the proportions of certain parts have been exaggerated to better illustrate details and features of the present disclosure.
Several definitions that apply throughout this disclosure will now be presented.
The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like.
The present disclosure is described in relation to a protection circuit 100.
The FIGURE illustrates an embodiment of the protection circuit 100, a power supply unit 200, and a device 300 which receives power from the power supply unit 200. The protection circuit 100 is coupled between the power supply unit 200 and the device 300. The protection circuit 100 can comprise a delay circuit 10, a power circuit 20, a switch circuit 30, and a determining circuit 40.
The delay circuit 10 can comprise a single chip U1. A power pin VCC of the single chip U1 is coupled to a power supply P3V3. A ground pin GND of the signal chip U1 is coupled to ground. A first input output pin P1 of the signal chip U1 is coupled to a signal pin B of the power supply unit 200 for receiving a power good signal from the power supply unit 200. A second input output pin P2 of the signal chip U1 is coupled to the switch circuit 30. When the first input output pin P1 of the signal chip U1 receives the power good signal, the second input output pin P2 of the signal chip U1 outputs the power good signal to the switch circuit 30 after a preset period of time.
The power circuit 20 can comprise resistors R1, R2 and an electronic switch Q1. A control terminal of the electronic switch Q1 is coupled to a voltage output pin A of the power supply unit 200 through the resistor R1. The control terminal of the electronic switch Q1 is also coupled to ground through the resistor R2. A first terminal of the electronic switch Q1 is coupled to the voltage output pin A of the power supply unit 200 for receiving a voltage signal from the power supply unit 200. A second terminal of the electronic switch Q1 is coupled to the determining circuit 40 and the device 300. The control terminal of the electronic switch Q1 is also coupled to the determining circuit 40.
The switch circuit 30 can comprise an electronic switch Q2. A control terminal of the electronic switch Q2 is coupled to the second input output pin P2 of the signal chip U1. A first terminal of the electronic switch Q2 is coupled to the power supply P3V3. A third terminal of the electronic switch Q2 is coupled to the determining circuit 40.
The determining circuit 40 can comprise resistors R3, R4, a Schmitt trigger U2, and a D trigger U3. An input terminal of the Schmitt trigger U2 is coupled to the second terminal of the electronic switch Q1 through the resistor R3. The input terminal of the Schmitt trigger U2 is also coupled to ground through the resistor R4. A power terminal of the Schmitt trigger U2 is coupled to the second terminal of the electronic switch Q2. A ground terminal of the Schmitt trigger U2 is coupled to ground. An output terminal of the Schmitt trigger U2 is coupled to an input terminal PRE of the D trigger U3. A clear terminal CLR of the D trigger U3 is coupled to the input terminal of the Schmitt trigger U2. A power terminal VCC of the D trigger U3 is coupled to the power terminal of the Schmitt trigger U2. A ground terminal GND of the D trigger U3 is coupled to ground. An output terminal Q of the D trigger U3 is coupled to the control terminal of the electronic switch Q1.
The electronic switch Q1 is turned on when the control terminal of the electronic switch Q1 receives the voltage signal from the voltage output pin A of the power supply unit 200. The power supply unit 200 supplies power to the device 300 through the first terminal and the second terminal of the electronic switch Q1. The first input output pin P1 of the signal chip U1 receives the power good signal from the signal pin B of the power supply unit 200, and the second input output pin P2 of the signal chip U1 outputs the power good signal to the switch circuit 30 after a preset period of time. When the switch circuit 30 receives the power good signal, the electronic switch Q2 is turned on. The power terminal of the Schmitt trigger U2 and the power terminal VCC of the D trigger U3 are energized by the power supply P3V3.
The input terminal of the Schmitt trigger U2 and the clear terminal CLR of the D trigger U3 receive a high level signal from the device 300 when the device 300 works normally. The input terminal PRE of the D trigger U3 receives a low level signal from the output terminal of the Schmitt trigger U2, and the output terminal Q of the D trigger U3 outputs a high level signal to the control terminal of the electronic switch Q1. The electronic switch Q1 is turned on continuously.
The input terminal of the Schmitt trigger U2 and the clear terminal CLR of the D trigger U3 receive a low level signal from the device 300 when the device 300 is short-circuited. The input terminal PRE of the D trigger U3 receives a high level signal from the output terminal of the Schmitt trigger U2, and the output terminal Q of the D trigger U3 outputs a low level signal to the control terminal of the electronic switch Q1. The electronic switch Q1 is turned off The power supply unit 200 is disconnected from the power to the device 300 and prevents the power supply unit 200 from shorting.
In at least one embodiment, the electronic switches Q1, Q2 can be N-channel field effect transistors.
The embodiment shown and described above is only an example. Many details are often found in the art such as the other features of a management device. Therefore, many such details are neither shown nor described. Even though numerous characteristics and advantages of the present technology have been set forth in the foregoing description, together with details of the structure and function of the present disclosure, the disclosure is illustrative only, and changes may be made in the detail, including in matters of shape, size and arrangement of the parts within the principles of the present disclosure up to, and including the full extent established by the broad general meaning of the terms used in the claims. It will therefore be appreciated that the embodiment described above may be modified within the scope of the claims.
Number | Date | Country | Kind |
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2013103307125 | Aug 2013 | CN | national |