Patent Application
20140078626
Many circuits are susceptible to electrical overstress as may relate to electrostatic discharge (ESD) or other overvoltage or overcurrent conditions that can be damaging. To address such overstress, protection circuits that generally operate like a switch are used to bypass/shunt current during an electrical overstress condition. In the case of an electrical overstress, such protection circuits switch to a low ohmic state, to connect an input (or other circuit) to a reference terminal such as a ground, common or lower-level power-rail terminal, thus shunting excessive charge to a place where it does not harm the IC.
Thyristor devices such as the silicon controlled rectifier (SCR) have been attractive as a protection device for a variety of applications. A common primary ESD protection device is the so-called “Low Voltage Triggered Silicon Controlled Rectifier,” or LVTSCR. This device is essentially a hybrid form of a grounded gate nmost (ggnmost) and a regular SCR, where the ggnmost is used to set the trigger voltage of the device. Such SCRs can take a high ESD-current density before failure (20-40 mA/μm), which results in a small device footprint if a given ESD robustness is required, and also in a low pin capacitance. Theoretically, it is possible to drive the gate of the nmost in the LVTSCR to produce an output signal. However, such LVTSCRs have exhibited high series resistance, and other implementation challenges. These and other matters have presented challenges to the implementation of SCRs and other circuit components with protection circuits, for a variety of applications.
Various example embodiments are directed to protection circuits and their implementation. According to an example embodiment, an apparatus includes a transistor, a thyristor having regions of alternating polarity including respective p-type anode and n-type cathode end portions separated by n-type and p-type base regions, and a resistor electrically connected between the drain of the transistor and the anode. The n-type base region is connected to the p-type anode region and the transistor's drain, and the p-type base region is connected to the n-type base region and the transistor's channel. The resistor is configured and arranged to forward bias a p-n junction between the p-type anode region and the n-type base region, in response to an electrostatic discharge condition (ESD) presented at the anode (or other overvoltage/overcurrent). In the forward-biased state, the thyristor shunts current between the anode and cathode.
Another example embodiment is directed to a self-protected output circuit having a signal-passing circuit including a transistor, a shunt circuit including a thyristor, and a resistor that switches the thyristor between current states. The transistor has source and drain regions and couples an output signal via the source and drain regions responsive to a signal presented to a gate of the transistor. The thyristor has contiguous, alternating regions of opposite polarity in a substrate with the source and drain, the alternating regions including a p-type anode connected to an n-type base including a highly-doped region that forms the drain, a p-type base connected to the n-type base and including a channel of the transistor between the source and drain, and an n-type cathode connected to the p-type base. The p-type anode has a heavily-doped p+ contact and a lesser-doped p-type region between the p+ contact and the n-type base, and the n-type cathode has a heavily-doped n+ contact and a lesser-doped n-type region between the n+ contact and the p-type base. The resistor electrically couples the drain and the p+ contact, and is responsive to a voltage presented at the p+ contact by switching the thyristor into high conductance state to shunt current between the p+ and n+ contacts, by forward biasing a p-n junction between the lesser-doped p-type region and the n-type base.
Another example embodiment is directed to an apparatus having a thyristor with regions of opposite polarity including an n-type cathode and a p-type anode separated by an n-type base region and a p-type base region. A cathode terminal is connected to the n-type cathode and the p-type base region, and an anode terminal is connected to the p-type anode. A gate communicates data by controlling a first one of the base regions respectively in high and low conductance states, to flow current between a second one of the base regions and one of the n-type cathode and p-type anode to which the first one of the base regions is connected. A resistor electrically connects the n-type base region and the anode terminal, with the resistor and thyristor being configured and arranged to forward bias a p-n junction between the p-type anode region and the n-type base region in response to an ESD condition (or other overvoltage condition) presented at the anode terminal, and the thyristor being responsive to the forward bias by shunting current between the anode terminal and the cathode terminal.
The above discussion/summary is not intended to describe each embodiment or every implementation of the present disclosure. The figures and detailed description that follow also exemplify various embodiments.
Various example embodiments may be more completely understood in consideration of the following detailed description in connection with the accompanying drawings, in which:
While various embodiments discussed herein are amenable to modifications and alternative forms, aspects thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure including aspects defined in the claims. In addition, the term “example” as used throughout this application is only by way of illustration, and not limitation.
Aspects of the present disclosure are believed to be applicable to a variety of different types of apparatuses, systems and methods involving protection circuits. While not necessarily so limited, various aspects may be appreciated through a discussion of examples using this context.
Various example embodiments are directed to a protection circuit that addresses conditions such as overvoltage/overcurrent conditions, and those referred to as electrostatic discharge (ESD) conditions. Certain embodiments are directed to a self-protected output circuit, in which an nmost inside the LVTSCR operates as a signal output device. In some implementations, an n-well connection is made in a LVTSCR with a connectivity including an explicit resistor that forward-biases an anode-base junction of the thyristor that facilitates such protection. With these approaches, robust ESD protection can be provided in a compact device. These and other embodiments address challenges, including those discussed in the above background discussion.
The resistor value and corresponding forward-biasing aspects can be tuned to suit particular applications. The resistor value is sufficiently large enough to forward-bias a p-plus/n-well junction (thyristor anode/n-base) during an ESD-strike, yet is low enough to allow the use of the nmost as an output device. In some implementations, the resistor value is about one order of magnitude lower than an inherent n-well resistor that is incorporated in the thyristor, to address ESD-strike conditions in which the current density inside a device is at least an order of magnitude larger than the current density during normal circuit operation. Using this approach, small nmost-based outputs can be made self-protecting against ESD-strikes, such as to render a 100 μm nmost robust protection against a 4 kV human body-model (HBM) strike.
In a more particular embodiment, ESD-type strikes are shunted between anode and cathode terminals via a thyristor, as controlled by a resistor that couples across and forward-biases a p-n junction between the anode and a corresponding n-base region of the thyristor. The device also includes a transistor having source and drain regions that are heavily-doped portions of an n-base and n+ cathode of the thyristor, and a channel in a p-base region of the thyristor between the source and drain. In some implementations the transistor operates to couple an output signal, and in certain embodiments has its gate coupled to the cathode terminal.
The transistor operates in a non-ESD mode to conduct current between the source and the anode terminal, via the resistor, at a voltage level that is below a voltage level at which the resistor forward-biases the p-n junction (e.g., under conditions in which the transistor operates to output a signal). The transistor operates responsive to an onset of the ESD condition, to conduct current between the anode and cathode terminals via the resistor, prior to the p-n junction becoming forward-biased, by flowing electron current to the cathode via the source and flowing hole current, generated via impact ionization at a p-n junction between the drain and p-type base region, to the cathode via the p-type base region, bypassing the source and channel. In response to the p-n junction becoming forward-biased, the thyristor shunts electron and hole current via thyristor operation of the p-type anode, n-type base region, p-type base region and n-type cathode while bypassing current flow via the channel region and the drain.
A more particular example embodiment is directed to a self-protected output circuit having a signal-passing circuit, a shunt circuit and a resistor that operates to couple a voltage to the signal-passing circuit and to operate the shunt circuit in a shunt condition in response to an overvoltage condition. The signal-passing circuit includes a transistor with source and drain regions in a substrate, the drain being coupled to the resistor, and via which an output signal is passed responsive to a signal presented to a gate of the transistor. The shunt circuit includes a thyristor having contiguous, alternating regions of opposite polarity, which are also in the substrate and include a p-type anode connected to an n-type base, a p-type base connected to the n-type base, and an n-type cathode connected to the p-type base. The p-type anode has a heavily-doped p+ contact and a lesser-doped p-type region between the p+ contact and the n-type base. The n-type cathode has a heavily-doped n+ contact and a lesser-doped n-type region between the n+ contact and the p-type base. The n-type base includes a highly-doped region that forms the drain, and the p-type base includes a channel via which the transistor passes current. The resistor switches the thyristor into a high conductance state in response to a high voltage at the p-type anode by forward-biasing a p-n junction between the lesser-doped p-type region and the n-type base.
The self-protected output circuit operates in a communication mode to conduct current between the resistor and the source via the drain and channel, at a voltage level that is below a threshold voltage level at which the resistor forward-biases the p-n junction. The self-protected output circuit also operates in an higher voltage/overvoltage onset mode, prior to the p-n junction being forward-biased, by conducting electron current between the resistor and the source via the drain and channel, and by conducting hole current between the resistor and the p+ contact via the drain and p-type base while bypassing the channel. In a very high overvoltage mode, the self-protected output circuit operates responsive to the p-n junction becoming a forward-biased, shunt hole current between the p+ and n+ contacts via the p-type anode, n-type base region and p-type base region, and shunt electron current between the n+ contact and each of the resistor and the p+ contact via the n-type base and p-type base.
Turning now to the figures,
Prior to the p-n junction between the p+ anode 110 and the n-type base 120 becoming forward-biased, the apparatus 100 operates to conduct current between the anode and cathode terminals 160/170 via the resistor 180. Such operation may be, for example, responsive to the onset of an ESD condition, during onset but before the forward-bias has been effected, or during normal operation (e.g., voltage across the resistor is insufficient to facilitate forward-biasing). In some embodiments, the apparatus 100 operates in such a state which the p-n junction is not forward-biased, to couple signals presented to the gate 150 by biasing the p-type base region 130 between the n+ cathode 140 and the n+ region 122 of the n-base 120, and conducting current via the resistor 180.
As discussed above, the apparatus 100 operates under different conditions to pass or shunt current, via one or more regions therein. In a more particular embodiment, the apparatus 100 operates in three modes. In a first mode (e.g., normal or non-ESD type of operation), the apparatus 100 conducts current between the source 140 and anode terminal 170, via the resistor 180, at a voltage level that is below a voltage level at which the resistor forward-biases the p-n junction. The apparatus 100 is responsive to an onset of the ESD condition in a second mode, to conduct current between the anode and cathode terminals 160/170 via the resistor 180, prior to the p-n junction becoming forward-biased, by flowing electron current to the cathode via the source 140 and by flowing hole current, generated via impact ionization at a p-n junction between the drain 122 and p-type base region 130, to the cathode terminal 160 via the p-type base region (bypassing the source and channel). In a third mode, the apparatus 100 operates in response to the p-n junction becoming forward-biased by shunting electron and hole current via thyristor operation of the p-type anode, n-type base region and p-type base region while bypassing current flow via the channel region (and, e.g., further bypassing the drain).
Beginning with
In
In
The current at which the device crosses over from the second to the third regime of operation exemplified in
Based upon the above discussion and illustrations, those skilled in the art will readily recognize that various modifications and changes may be made to the various embodiments without strictly following the exemplary embodiments and applications illustrated and described herein. For example, differently-doped regions can be implemented to effect current flow as described herein, and circuits implemented for signal-passing can be effected as protection circuits (e.g., without signal-passing and/or connecting the transistor gate to a cathode terminal). Such modifications do not depart from the true spirit and scope of various aspects of the invention, including aspects set forth in the claims.
