Claims
- 1. Apparatus for protecting the contents of a plurality of memory devices in a microprocessor system comprising a central processing unit, bus means and a plurality of memory devices communicating with said unit through said bus means, each of said memory devices having a power supply voltage input terminal and a disabling input terminal, said apparatus comprising:
- a power source generating an A.C. output;
- means for converting the output of said A.C. power source to a D.C. signal;
- a D.C. battery source;
- a common terminal for coupling D.C. power to the power supply voltage input terminal of at least one of said memory devices;
- said D.C. signal being coupled to said common terminal;
- said battery source being coupled to said common terminal through first switch means;
- said switch means being normally open and including a control input for selectively coupling said battery to said common terminal;
- first means responsive to the D.C. signal of said converting means for generating a first control signal, a first predetermined time interval after said D.C. signal has dropped to a predetermined level;
- said control input being responsive to said first control signal for closing the normally open switch means;
- second means responsive to said D.C. signal for generating a second control signal a second predetermined time interval after said D.C. signal has dropped to said predetermined level and means responsive to said second control signal for coupling the disabling input terminals of said memory devices to said battery source, said second predetermined time interval being greater than said first predetermined time interval whereby battery power is applied to said memory devices before said memory devices are disabled to permit said central processing unit to save operating information.
- 2. The apparatus of claim 1 wherein said battery source is rechargable and further comprising means for energizing the central processing unit from said D.C. signal; normally open second switch means connected between said converting means and said battery source, and means for closing said switch when the central processing unit is energized to charge said battery.
- 3. The apparatus of claim 1 further comprising third means responsive to said D.C. signal for generating a third control signal a third predetermined time interval after the level of said D.C. signal has dropped to said first predetermined level;
- said central processing unit including means responsive to said third control signal for deactivating said central processing unit.
- 4. The apparatus of claim 1 wherein said second predetermined time interval is less than said third predetermined time interval and is greater than said first predetermined time interval.
- 5. The apparatus of claim 3 wherein upon turn on of said central processing unit the first and second and third control signals are altered at fourth and fifth and sixth time intervals after said D.C. signal increases to a second predetermined level;
- said first D.C. signal responsive means shunting a common terminal coupled to the memory devices after said fifth time interval and said third D.C. signal-responsive means reactivating said central processing unit after said sixth time interval.
- 6. The apparatus of claim 1 wherein the second means includes semiconductor means powered by power delivered by said common terminal for coupling the disabling input terminals of said memory devices to said battery source.
- 7. The apparatus of claim 6 further comprising diode means for coupling said D.C. signal from said conversion means to said common terminal and being poled to prevent the output from the battery source from being fed back to said conversion means.
- 8. The apparatus of claim 1 further comprising:
- second conversion means for converting the A.C. source output to a second D.C. signal, the second D.C. signal being coupled through a diode to said common terminal;
- said common terminal being connected to the power input terminals of said memory devices.
- 9. Apparatus for protecting the contents of random access memory devices in a system having an on/off switch in a power down condition comprising:
- an A.C. power source;
- conversion means coupled to said A.C. power source for generating at least first, second and third D.C. outputs;
- a rechargeable battery source;
- first switch means having control means responsive to turn on of said system on/off switch for coupling the battery source to said first D.C. output;
- a common terminal;
- diode means for coupling the second D.C. output to said common terminal;
- second switch means having control means for selectively coupling the battery source to said common terminal;
- first control signal generating means coupled to said third D.C. output for generating a first control signal a predetermined time interval after the said third D.C. output drops below a pedetermined level;
- said control means of said second switch means coupling said battery source to said common terminal responsive to said first control signal;
- second control signal generating means for generating a second control signal a predetermined time after said third D.C. output drops to said predetermined level;
- third switch means powered by power from said common terminal and having a control input responsive to said second control signal for generating a memory control output;
- said memory devices having a power input coupled to said common terminal and having an enable input coupled to the common terminal through a resistor;
- switch means for shunting said enable terminal to ground responsive to said memory control output.
- 10. A circuit for monitoring a power source to protect a system comprising a microprocessor and memory devices coupled thereto comprising:
- an A.C. power source having an output;
- means for converting the output of the power source to a plurality of D.C. outputs;
- a rechargeable battery supply;
- first switch means for coupling said A.C. power source to said converting means;
- second switch means responsive to closing of said first switch means for coupling said battery supply to said one of said D.C. outputs;
- said memory devices having a power input;
- a common terminal coupled to said power input;
- third switch means coupled between said battery source and said common terminal;
- a first capacitor;
- first circuit means coupling said first capacitor to one of said D.C. outputs to charge said first capacitor;
- second circuit means for discharging said first capacitor;
- a second capacitor;
- third circuit means coupling said second capacitor to one of said D.C. outputs to charge said second capacitor at a given rate;
- fourth circuit means for discharging said second capacitor at a rate which is greater than said given rate;
- the arrangement being such that said first capacitor is charged and discharged faster than is the second capacitor;
- said third switch means including control means responsive to discharge of said first capacitor to a predetermined level for coupling said battery supply to said common terminal;
- and means responsive to discharge of said second capacitor to a predetermined level for disabling said memory devices.
- 11. The monitoring circuit of claim 10 wherein said memory devices include random access memory locations having contents and means responsive to said control means for saving the contents of said memory locations.
- 12. The monitoring circuit of claim 10 in which at least one of said memory devices has a read/write input terminal, and in which said means responsive to discharge of said second capacitor comprises means for coupling said read/write input terminal to said common terminal.
- 13. The monitoring circuit of claim 10 in which the memory devices have enable terminals and in which said means responsive to discharge of said second capacitor includes means for coupling a disabling signal to said enable terminals.
- 14. The monitoring circuit of claim 13 including means for opening said third switch when said first capacitor charges to a second predetermined level during a power up mode.
- 15. The monitoring circuit of claim 14 including means for removing said disable signal from said memory devices when said second capacitor charges to said second predetermined level during a power up mode.
Parent Case Info
This is a division of application Ser. No. 699,055, filed Feb. 7, 1985.
US Referenced Citations (12)
Divisions (1)
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Number |
Date |
Country |
Parent |
699055 |
Feb 1985 |
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