Patent Application
20160094442
The present invention relates to network switches and switching, and more particularly, this invention relates to protocol independent multicast (PIM) multicast register message transmission control in a virtual link aggregation group (vLAG) topology.
In a data center comprising one or more access switches, each access switch connects two aggregation switches for redundancy. Link aggregation uses available bandwidth across a switch boundary at an aggregation layer.
Embodiments of the invention relate to register message transmission control in a system. One embodiment includes forwarding a communication packet to a first switch. A multicast source route entry is created by the first switch based on the communication packet. The communication packet is forwarded from the first switch to a second switch. A duplicate of the multicast source route entry is created by the second switch based on the forwarded communication packet. A register message is sent to a router by one of the first switch and the second switch based on a first vLAG role. Sending of a duplicate of the register message by one of the first switch and the second switch is prevented based on a second vLAG role.
Another embodiment comprises a system including an access switch that receives a communication packet from a multicast source. A first vLAG switch receives the communication packet from the access switch and extracts a multicast source route entry from the received communication packet. A second vLAG switch receives the communication packet from the first vLAG switch and extracts the multicast source route entry from the received communication packet. One of the first vLAG switch and the second vLAG switch sends a register message to a router based on vLAG roles. One of the first vLAG switch and the second vLAG switch is prevented from sending a duplicate of the register message to the router based on a particular vLAG role.
One embodiment comprises a computer program product for register message transmission control over a link aggregation group (LAG). The computer program product comprising a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. The program instructions executable by an access switch to cause the access switch to perform a method comprising: forwarding, by the access switch, a communication packet to a first virtual link aggregation group (vLAG) switch. The first vLAG switch creates a multicast source route entry based on the communication packet. The first vLAG switch forwards the communication packet to a second vLAG switch. The second vLAG switch creates a duplicate of the multicast source route entry based on the forwarded communication packet. A register message is sent to a router by one of the first vLAG switch and the second vLAG switch based on vLAG roles. Sending of a duplicate of the register message by one of the first vLAG switch and the second vLAG switch is prevented based on a particular vLAG role.
Other aspects and embodiments of the present invention will become apparent from the following detailed description, which, when taken in conjunction with the drawings, illustrate by way of example the principles of the invention.
Referring now to the drawings,
In use, the gateway 101 serves as an entrance point from the remote networks 102 to the proximate network 108. As such, the gateway 101 may function as a router, which is capable of directing a given packet of data that arrives at the gateway 101, and a switch, which furnishes the actual path in and out of the gateway 101 for a given packet.
Further included is at least one data server 114 coupled to the proximate network 108, which is accessible from the remote networks 102 via the gateway 101. It should be noted that the data server(s) 114 may include any type of computing device/groupware. Coupled to each data server 114 is a plurality of user devices 116. Such user devices 116 may include a desktop computer, laptop computer, handheld computer, printer, and/or any other type of logic-containing device. It should be noted that a user device III may also be directly coupled to any of the networks, in some embodiments.
A peripheral 120 or series of peripherals 120, e.g., facsimile machines, printers, scanners, hard disk drives, networked and/or local storage units or systems, etc, may be coupled to one or more of the networks 104, 106, 108. It should be noted that databases and/or additional components may be utilized with, or integrated into, any type of network element coupled to the networks 104, 106, 108. In the context of the present description, a network element may refer to any component of a network.
According to some approaches, methods, and systems described herein may be implemented with and/or on virtual systems and/or systems which emulate one or more other systems, such as a UNIX system which emulates an IBM z/OS environment, a UNIX system which virtually hosts a MICROSOFT WINDOWS environment, a MICROSOFT WINDOWS system which emulates an IBM z/OS environment, etc. This virtualization and/or emulation may be enhanced through the use of VMWARE software, in some embodiments.
In other examples, one or more networks 104, 106, 108, may represent a cluster of systems commonly referred to as a “cloud.” In cloud computing, shared resources, such as processing power, peripherals, software, data, servers, etc., are provided to any system in the cloud in an on-demand relationship, therefore allowing access and distribution of services across many computing systems. Cloud computing typically involves an Internet connection between the systems operating in the cloud, but other techniques of connecting the systems may also be used, as known in the art.
In one example, the workstation may have resident thereon an operating system such as the MICROSOFT WINDOWS Operating System (OS), a MAC OS, a UNIX OS, etc. It will be appreciated that other examples may also be implemented on platforms and operating systems other than those mentioned. Such other examples may include operating systems written using JAVA, XML, C, and/or C++ language, or other programming languages, along with an object oriented programming methodology. Object oriented programming (OOP), which has become increasingly used to develop complex applications, may also be used.
According to an embodiment of the invention, PIM register message transmission control is provided in a system having a vLAG topology. One embodiment includes forwarding a communication packet to a first switch. A multicast source route entry is created by the first switch based on the communication packet. The communication packet is forwarded from the first switch to a second switch. A duplicate of the multicast source route entry is created by the second switch based on the forwarded communication packet. A register message is sent to a router by one of the first switch and the second switch based on vLAG primary and secondary roles. Sending of a duplicate of the register message by one of the first switch and the second switch is prevented.
Since vLAG is an extension to standard link aggregation, layer 2 and layer 3 features may be supported on top of vLAG. In the system 300 shown in FIG, 3, both primary aggregator switch 302 and secondary aggregator switch 304 have PIM enabled. PIM uses a routing table to discover whether a multicast packet has arrived on the correct interface. The multicast source entries include (S, G) information, where S represents an Internet Protocol (IP) address of a source device, and G represents a group address.
In vLAG PIM topology with a multicast source 310 connected to the vLAG ports, when multicast traffic is received by primary aggregator (vLAG) switch 302 and the secondary aggregator (vLAG) switch 304, both the primary aggregator (vLAG) switch 302 and the secondary aggregator (vLAG) switch 304 will create the multicast route entry regardless of a DR/Non-DR interface. In conventional systems, both the primary aggregator (vLAG) switch 302 and the secondary aggregator (vLAG) switch 304 will send the register message to the upstream multicast (PIM-RP) router 320 because both vLAG switches will act as first hop routers for the received multicast traffic. This will make the upstream multicast router 320 forward duplicate multicast packets to the receiver(s) 330 in shared path tree. Additionally, the upstream multicast router 320 may receive unwanted register messages continuously from one of the vLAG switches.
In one embodiment, only the primary vLAG switch will send the register message to the upstream multicast router 320 regardless of DR/Non-DR, and the register message is prevented/controlled from being sent by the secondary vLAG switch. In one embodiment; upon receiving the multicast traffic 341, the secondary vLAG switch creates the multicast route entry as per the PIM protocol, but the secondary vLAG switch will not send a register message to the upstream multicast router 320. In one embodiment, when the primary vLAG switch is down/failed, the secondary vLAG switch will become the primary vLAG switch and will start to send the register message to the upstream multicast router 320. In one embodiment, advantages of this approach over the conventional systems includes preventing unnecessary register messages from being sent to the PIM-RP router (e.g., upstream multicast router 320); and no special communication is required between the primary vLAG switch, secondary vLAG switch and the PIM-RP router.
In this example embodiment, since both vLAG switches are first hop routers and do not have DR/Non-DR interfaces in the vLAG switches, both vLAG switches will create multicast route entries and instead of both vLAG switches trying to send the register message to the router 320 (e.g., PIM-RP router), to avoid duplicate register messages on the shared path and ensure PIM protocol compliance, only the primary vLAG switch is permitted to send a register message 343 to the router 320 (which in this example is the second vLAG switch (primary aggregator switch 302)). The first vLAG switch (i.e., secondary aggregator switch 304) is thus, not permitted to send a register message 343 to the router 320. In one embodiment, the control of forwarding the register message 343 transmission does not prohibit other traffic communications. Therefore, after the PIM topology settles, either the primary or secondary vLAG switch can send native multicast data traffic to the receiver based on shortest path tree. In one embodiment; in the case where the primary vLAG switch is down or failed, the secondary vLAG switch will become the primary vLAG switch and will send a register message 343 to the router 320. In one embodiment, the primary vLAG switch forwards traffic 343 to the upstream multicast router 320 for forwarding to at a receiver 330.
As shown in
In one embodiment, in process 400, the first switch and the second switch are part of a vLAG topology, and the communication packet is forwarded to the first switch based on LAG hashing. In one embodiment, in process 400, the second switch forwards communication traffic to a multicast router (e.g., multicast router 320,
In one embodiment, for process 400 the first switch or the second switch is a primary vLAG switch, and if the second switch fails, the first switch becomes the primary vLAG switch In one example embodiment, the first switch and the second switch each comprise a first hop router.
According to various embodiments, the process 400 may be performed by a system, computer, or some other device capable of executing commands, logic, etc., as would be understood by one of skill in the art upon reading the present descriptions.
According to the embodiments and approaches described herein, unnecessary register messages sent to a PIM-RP are prevented, and no special communication is required between the vLAG Primary switch, secondary switch and the PIM-RP router.
The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.
The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in. any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.
Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.
These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed.
Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
