Patent Application
20230252214
This disclosure relates generally to the field of semiconductor devices, and more specifically, to integrated circuit (IC) devices.
For the past several decades, the scaling of features in ICs has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. Buried power rails (BPRs) can be a key scaling booster for complementary metal-oxide-semiconductor (CMOS) extension, e.g., beyond the 5-nm node.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
The systems, methods, and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
For purposes of illustrating providing fill patterns for IC devices, proposed herein, it might be useful to first understand phenomena that may come into play in such structures. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.
Relentless scaling of transistors and wires in advanced semiconductor technologies has not only resulted in major process-related challenges but has also imposed severe design challenges in the sub-5 nm technology regime. Dimensional scaling of designs has been made possible by (i) Front-End-of-Line (FEOL) and Back-End-of-Line (BEOL) pitch scaling, which worsens short-channel effects in transistors and increases wire/contact resistances; and, (ii) fin depopulation in logic cells, which causes degradation of transistor drive. To enable further area scaling in sub-5 nm nodes, an approach of burying the power rails into the substrate has been proposed, which no longer requires reserving two routing tracks for power nets (e.g., VDD or VSS) in the logic cell area. Additionally, these BPRs can achieve a higher aspect ratio, thus, exhibiting lower resistance than local level BEOL power rails. BPRs can be a key scaling booster for CMOS extension beyond the 5-nm node. Power lines which conventionally run outside substrates can be replaced with power lines “buried” within substrates, e.g., within a shallow trench isolation (STI) layer and Si substrate. Such power lines are called BPRs. A BPR is a power rail that is at least partially buried in a support structure, e.g., a substrate, die, etc. A BPR includes an electrically conductive material, such as metal. A rail can have an elongated structure having a longitudinal axis as an axis along which a dimension of the rail is typically the longest (e.g., compared to dimensions of the rail along other two axes that may be used to define a three-dimensional configuration of the rail, where cross-sections of the rail along various planes that are perpendicular to the longitudinal axis are transverse cross-sections). The longitudinal axis may be parallel to the frontside surface or the backside surface of the support structure. BPR frees up routing resources, which results in logic cell height reduction and overall area scaling.
The BPR technologies bring very thick metals lines near to active devices. Since metals like copper, aluminum, and tungsten have higher thermal expansion coefficients than silicon, this can result in inhomogeneous mechanical stress, resulting in a shift of mobility in the active devices. This effect is also observed from thick metal in CMOS technologies, resulting in change of current. Since BPR brings thick metals even closer, an even larger change is expected, which can be critical for high precision analog circuits. Some solutions attempting to address these challenges include providing fill patterns in IC devices. A fill pattern may include one or more fill structures, where a fill structure is a non-functional structure that is added to an IC device to facilitate fabrication of the IC device. For instance, a fill structure can release stress, improve density uniformity, prevent dishing, etc. during fabrication. Fill structures can have various shapes, such as rectangles, polygons, etc. Fill structures can include various materials, such as metal, oxide, other types of materials, or some combination thereof.
The existing fill solutions can further introduce unwanted asymmetries to differential or array circuits. The existing fill procedures are usually optimized for the process requirements but do not count in layout and design symmetries. The existing fill procedures can create different sized fill structures, which are often placed opportunistically on a staggered pattern. Those introduced asymmetries results in degraded circuit performance, such as asymmetric capacitances, offset voltages for analog, the generation of harmonic frequencies for RF (radio frequency) and mmWave (millimeter wave) circuits, etc. Therefore, improved fill approaches are needed to preserve the intended layout symmetry.
Embodiments of the present disclosure relate to computer-implemented methods for providing fill patterns for IC devices that may improve on at least some of the drawbacks and challenges described above, as well as the resulting devices and systems.
An example computer-implemented method includes detecting a first device and a second device in an IC device. The first device and second device are functional. For instance, the first or second device is a functional component in the IC device, such as an electronic component. A line is generated based at least on the first device and the second device. The line divides the IC device into a first section, in which the first device is located, and a second section, in which the second device is located. The second device is transformed into a structure in the first section, e.g., through a reflection transformation across the line. The structure is merged with the first device to form a merged structure. A shape of the merged structure may be the shape of the first device or the shape of the structure. Alternatively, the shape of the merged structure is a combination of the shape of the structure and the shape of the first device. A first fill pattern is generated based on the merged structure. The first fill pattern includes fill structures in the first section. A second fill pattern is generated based on the first fill pattern. The second fill pattern includes fill structures in the second section. The second fill pattern may be a mirror image of the first fill pattern across the line.
Another example computer-implemented method includes generating a fill pattern in an IC device and analyzing an impact of the fill pattern on a first device or a second device in the IC device. The fill pattern includes fill structures surrounding at least a portion of the first device and at least a portion of the second device. The impact includes mechanical stress (e.g., mechanical stress exerted by fill structures on the first or second device), electrical coupling (e.g., electrical coupling between fill structures and the first or second device, or electrical coupling between the first device and the second device), magnetic coupling (e.g., magnetic coupling between fill structures and the first or second device, or magnetic coupling between the first device and the second device), thermal coupling (e.g., thermal coupling between fill structures and the first or second device, or thermal coupling between the first device and the second device), other types of impact, or some combination thereof. A critical region in the IC device is determined based on the impact. Further, one or more fill structures in the critical region are modified to reduce or minimize the impact.
Embodiments of the present disclosure provide fill patterns that may preserve layout symmetry of IC devices. The fill patterns can minimize asymmetries with high reproducibility. The fill patterns can also reduce impacts of fill structures on active devices and thereby enables higher reliability and performance of those devices.
IC devices as described herein, in particular IC devices with fill patterns as described herein, may be used for providing electrical connectivity to one or more components associated with an IC or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.
For purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details or/and that the present disclosure may be practiced with only some of the described aspects. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
Further, references are made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, if a collection of drawings designated with different letters are present, such a collection may be referred to herein without the letters.
In the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, this is simply for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the manufacturing processes used to fabricate semiconductor device assemblies. Therefore, it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using, e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Furthermore, although a certain number of a given element may be illustrated in some of the drawings (e.g., a certain number of devices, a certain number of fill structures, etc.), this is simply for ease of illustration, and more, or less, than that number may be included in an IC device with fill structures as described herein. Still further, various views shown in some of the drawings are intended to show relative arrangements of various elements therein. In other embodiments, various IC devices with fill structures as described herein, or portions thereof, may include other elements or components that are not illustrated (e.g., transistor portions, various components that may be in electrical contact with any of the transistors, etc.). Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using, e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., Physical Failure Analysis (PFA) would allow determination of presence of IC devices with fill structures as described herein.
Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. These operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.
The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. The terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side” to explain various features of the drawings, but these terms are simply for ease of discussion, and do not imply a desired or required orientation. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.
For example, some descriptions may refer to a particular source or drain region or contact being either a source region/contact or a drain region/contact. However, unless specified otherwise, which region/contact of a transistor is considered to be a source region/contact and which region/contact is considered to be a drain region/contact is not important because under certain operating conditions, designations of source and drain are often interchangeable. Therefore, descriptions provided herein may use the term of a “S/D” region/contact to indicate that the region/contact can be either a source region/contact, or a drain region/contact.
In another example, if used, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die,” the term “insulating” means “electrically insulating,” the term “conducting” means “electrically conducting,” unless otherwise specified. Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, “an electrically conductive material” may include one or more electrically conductive materials.
In another example, if used, the terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc., the term “high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide, while the term “low-k dielectric” refers to a material having a lower dielectric constant than silicon oxide.
In yet another example, a term “interconnect” may be used to describe any element formed of an electrically conductive material for providing electrical connectivity to one or more components associated with an IC or/and between various such components. In general, the “interconnect” may refer to both conductive lines/wires (also sometimes referred to as “lines” or “metal lines” or “trenches”) and conductive vias (also sometimes referred to as “vias” or “metal vias”). In general, a term “conductive line” may be used to describe an electrically conductive element isolated by a dielectric material typically comprising an interlayer low-k dielectric that is provided within the plane of an IC chip. Such conductive lines are typically arranged in several levels, or several layers, of metallization stacks. On the other hand, the term “conductive via” may be used to describe an electrically conductive element that interconnects two or more conductive lines of different levels of a metallization stack. To that end, a via may be provided substantially perpendicularly to the plane of an IC chip or a support structure over which an IC device is provided and may interconnect two conductive lines in adjacent levels or two conductive lines in not adjacent levels. A term “metallization stack” may be used to refer to a stack of one or more interconnects for providing connectivity to different circuit components of an IC chip.
Furthermore, the term “connected” may be used to describe a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” may be used to describe either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” may be used to describe one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.
The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20% of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−5-20% of a target value based on the context of a particular value as described herein or as known in the art.
The support structure 110 may be any suitable structure with which the device 120 can be associated. For instance, the support structure 110 may be a substrate, a die, a wafer, or a chip. In some embodiments, the support structure 110 may be a printed circuit board (PCB) substrate. In other embodiments, the support structure 110 is a semiconductor substrate, which is composed of semiconductor material systems including, for example, n-type or p-type materials systems. One or more transistors may be built on the support structure 110. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V, group II-VI, or group IV materials. In some embodiments, the substrate may be non-crystalline.
Although a few examples of materials from which the support structure 110 may be formed are described here, any material that may serve as a foundation upon which IC devices implementing fill patterns as described herein may be built falls within the spirit and scope of the present disclosure. In various embodiments, the support structure 110 may include any such substrate material that provides a suitable surface for forming the fill pattern. The support structure 110 may, e.g., be the wafer 2000 of
The device 120 is a functional component. The device 120 may perform an electronic function in the IC device 100. In some embodiments, the device 120 is an electronic component, such as a transistor, capacitor, resistor, power rail, wire, bus, and so on. In other embodiments, the device 120 is a collection of multiple electronic components, such as an amplifier, oscillator, timer, microprocessor, memory, and so on. The device 120 is associated with the support structure 110. In an embodiment, at least a portion of the device 120 is in the support structure 110. In another embodiment, the device 120 is attached on a surface of the support structure 110. In yet another embodiment, the device 120 is associated with the support structure 110 in other ways. For instance, the device 120 is coupled to the support structure 110 through another component, such as a via, a layer, etc.
A fill structure 130 is a non-functional structure that is added to the IC device 100 to facilitate fabrication of the IC device 100. For instance, the fill structures 130 can release stress, prevent dishing, facilitate uniform density, or provide other types of benefits during the fabrication. A fill structure 130 may be referred to as a dummy fill or floating fill in the IC device 100. In some embodiments, a fill structure 130 is not connected to any of a signal source, a power source, or a reference potential during operation of the IC device 100. For purpose of simplicity and illustration, the fill structures 130 are rectangular structures with various sizes. In other embodiments, the fill structures 130 can have other shapes. The fill structure 130 may be a structure of a metal, oxide, or other types of materials. The fill structures 130 are around the device 120, e.g., the fill structures 130 are located at one or more sides of the device 120. In the embodiment of
The fill pattern is generated by identifying a filling space in the IC device 100. The filling space is the space in the IC device 100 that are not occupied by the device 120 (or other devices, if any). The fill pattern can be placed in a portion of, or the whole of, the filling space. In some embodiments, the fill pattern is generated based on one or more fill rules. A fill rule specifies a requirement for the fill pattern. Example fill rules may specify, for instance, shapes of fill structures, sizes of fill structures, pitches of fill structures (i.e., the distance between two adjacent fill structures), enclosures of fill structures (i.e., distances from fill structure to functional devices), layers (e.g., FEOL, BEOL, or BPR layers) where fill structures are placed, and so on. The fill rules can be a predetermined fixed set of rules, which is slightly adjusted regarding the device 120. In
However, the placement of the fill pattern can influence performance of the device 120.
Even though not shown in
As shown in
Further, a line 215 is defined in the image 200. The line 215 may not represent any real components in the IC device. In some embodiments, the line 215 may be a symmetry axis of the IC device or of the image 200, or be a line crossing a symmetry point of the IC device. The symmetry axis of the IC device may be a symmetry axis of the support structure, a symmetry axis of some or all the devices, or a combination of both. In some embodiments, the line 215 is determined based on one or more pairs of objects 220. One example pair is the objects 220C and 220C′. The line 215 is determined as a symmetry axis of the pair, e.g., the object 220C is a mirror image of the object 220C′ across the line 215. Another example pair can be the objects 220A and 220A′, or the objects 220B and 220B′. The line 215 is in the middle of the objects 220A and 220A′ or the middle of the objects 220B and 220B′. The line 215 divides the image 200 into two sections 203 and 207. One or more dimensions of the section 209 can be the same as the corresponding dimensions of the section 207. In some embodiments, the section 209 has the same size as the section 207.
In
Alternatively, a structure 230 may be generated based on multiple objects 220 through transformation and merging. For example, the structure 230A is generated based on the objects 220A and 220A′. The object 220A is transformed to a structure (not called out in
In the image 201, each structure 230 is a mirror image of another structure 230 across the line 215. For instance, the structure 230A is a mirror image of the structure 230A′ across the line. Similarly, the structure 230B is a mirror image of the structure 230B′ across the line and the structure 230C is a mirror image of the structure 230C′ across the line. A structure 230 may have the same shape, size, and location as the object 220, from which the structure 230 is transformed. For instance, the structure 230C has the same shape, size, and location as the object 220C. Alternatively, a structure 230 may have a different shape, size, or even location as the object 220 from which the structure 230 is transformed. For instance, the structure 230A has a different shape and size from the object 220A.
A structure 230 may have a shape that is a combination of the shapes of two objects 220. The two objects 220 are at opposite sides of the line 215. For instance, the shape of the structure 230A is a combination of the shape of the object 220A and the shape of the object 220A′. Also, the shape of the structure 230B is a combination of the shape of the object 220B and the shape of the object 220B′. The image 201 has line symmetry across the line 215. Such a structure 230 can be formed by combining or merging the two objects 220.
In
In some embodiments, in order to enable a symmetric filling, the formation of the original fill pattern in
After the regions of interest 260 and 265 are identified, one or more qualities of the fill structures 250 in the regions of interest 260 and 265 are determined and compared. A quality of a region of interest may be determined based on the fill structures 250 in the region of interest and one or more objects 220 associated with the region of interest, e.g., the objects 220 based on which the region of interest is identified. In an embodiment, the quality relates to distances from the fill structures 250 to the objects 220, such as an average or sum of the distances of individual ones of the fill structures 250 to individual ones of the objects 220. The average or sum may be a weight average or sum. For instance, an object 220 may have a higher weight than another object 220. In another embodiment, the quality is a mechanical stress exerted by the fill structures 250 on the objects 220. In yet another embodiment, the quality is a coupling (e.g., electrical coupling, thermal coupling, magnetic coupling, etc.) between the fill structures 250 and the objects 220. In yet another example, the quality is a size of the fill structures 250, e.g., an average of the sizes of the fill structures 250, a sum of the sizes of the fill structures 250, a weighted average of the sizes of the fill structures 250, or a weighted sum of the sizes of the fill structures 250. The quality of the region of interest 260 is compared with the quality of the region of interest 265. The section that has the region of interest having the better quality is selected as the source section. In some embodiments, the better quality is longer distance from the fill structures 250 to the objects 220, lower mechanical stress, less coupling, or smaller size of the fill structures 250.
In the embodiment of
In
In
In
In the embodiment of
The total fill pattern for the IC device 400 includes the fill patterns in all the segments 441, 442, 443, 444, and 445. By separating the filling region into segments based on the symmetry axes and filling the segment individually, the total fill pattern for the IC device 400 achieves a high symmetry, leading to an identical (or almost identical) influence of the fill structures on each of the devices 420 and 430.
A device can be influence not only by fill structures on the same layer, but also by fill structures on another layer that is either above or below the device.
In the embodiments shown in the figures described above, the symmetry axes are in the center of the filling region. However, in other embodiments, the symmetry axes might not be in the center of the filling region of an IC device, or an IC device may include filling regions of different sizes.
In
In
In
The process illustrated in
In some embodiments, the critical regions are identified based on a redefined set of boundary conditions. The predefined boundary conditions include but are not limited to mechanical stress levels at certain regions, electrical coupling between a device and fill structures, electrical coupling between different devices, thermal coupling between a device and fill structures, magnetic coupling between a device and fill structures, etc. In an example, the critical regions 1050 and 1060 are identified on the ground that fill structures 1040 around the device 1030 (i.e., the fill structures 1040 in the critical regions 1050 and 1060) are asymmetric. The critical regions 1055 and 1065 are identified on the ground that the electrical coupling between the devices 1020 and 1030 is different from the electrical coupling between the devices 1010 and 1030. The critical regions 1070 and 1075 are identified on the ground that a stress profile around the devices 1010 and 1020 are uneven.
The fill rules are then adjusted to reduce the influence of the fill structures 1040 in the critical regions.
However, it is possible that a fill rule may benefit one critical region but impair another critical region. For instance, a fill rule may reduce the influence of the fill structures 1040 in one critical region but increases the influence of the fill structures 1040 in another critical region. In some embodiments, a weight is determined for a boundary condition, e.g., based on the importance of the boundary condition to the performance of one or more devices or the performance of the IC device 1000 as a whole. A boundary condition having a higher weight is given a higher priority and fill rules that address the boundary condition will trump fill rules that address another boundary condition that has a lower weight.
In some embodiments, the process illustrated in
In some embodiments, a process of adjusting fill patterns includes both horizontal adjustment and vertical adjustment. In some embodiments, an initial fill pattern is formed on each layer. Next, critical regions are identified through simulation based on boundary conditions. Further, fill rules are adjusted based on each boundary conditions. Then the adjusted fill rules are optimized based on weights of the boundary conditions. One or more layers are refilled with the optimized fill rules. The steps of identifying critical region, adjusting fill rules, and optimizing fill rules can be iterated until a certain confidence threshold is reached.
In
The method 1300 includes detecting 1310 a first object and a second object in an image. The image represents the IC device. The first object represents a first device in the IC device. The second object represents a second device in the IC device. The image may be two-dimensional or three-dimensional. In some embodiments, the image is a virtual representation of the IC device that is generated by a computing device. The image can include other objects that represent other components of the IC devices, such as other devices, a support structure associated with one or more devices in the IC device, layers in the IC device, etc.
A device (e.g., the first device or the second device) can be a functional component of the IC device. A device may perform an electronic function in the IC device. In some embodiments, a device is an electronic component, such as a transistor, capacitor, resistor, power rail, wire, bus, and so on. In other embodiments, a device includes a collection of multiple electronic components, such as an amplifier, oscillator, timer, microprocessor, memory, and so on.
The method 1300 further includes defining 1320 a line in the image based on the first object and the second object. The line may be defined by identifying a symmetry axis or symmetry point of the IC device. The line can be the symmetry axis or a line crossing the symmetry point. In some embodiments, the line is in the middle of a pair of devices in the IC device. For instance, the line is in the middle of at least a portion of the first object and at least a portion of the second object. The IC device comprises a first section that is on a first side of the line and a second section that is on a second side of the line. The second side is opposite the first side. The first object at least partially located in a first section, and the second object at least partially located in the second section. An example of the line is the line 215, 505, 605, 740, or 805.
The method 1300 further includes generating 1330 a first structure based on the first object and generating 1340 a second structure based on the second object. The first structure is a mirror image of the second structure across the line. The first structure may have the same (or substantially same) location as the first object in the first section. The second structure may have the same (or substantially same) location as the second object in the second section. In some embodiments, a structure is generated by transforming an object, merging multiple objects, or both. A transformation may be a direct transformation (e.g., moving or copying), a reflection transformation (e.g., across the line), a rotational transformation (e.g., around a predetermined angle), etc.
In an example, the first structure is the structure 230A, which is transformed from the object 220A, and the second structure is the structure 230A′, which is transformed from the object 220A′. The structure 230A is formed by merging a structure that is copied from the object 220A with a mirror image of the object 220A′ across the line 215. The structure 230A′ is copied from the object 220A′. The structure 230A is a mirror image of the structure 230A′. In another example, the first structure is the structure 230B, which is transformed from the object 220B, and the second structure is the structure 230B′, which is transformed from the object 220B′. The structure 230B is formed by merging the structure 2256, which is copied from the object 220B, with the structure 2256′, which is formed through a reflection transformation of the object 220B′. The structure 230B′ is a mirror image of the structure 230B. In yet another example, the first structure is the structure 230C, which is transformed from the object 220C, and the second structure is the structure 230C′, which is transformed from the object 220C′. The structure 230C is formed by copying the object 220C. The structure 230C is formed by copying the object 220C′. The structure 230C′ is a mirror image of the structure 230C.
The method 1300 further includes generating 1350 a first fill pattern for the first section based on the first structure. The first fill pattern comprises a first fill structure in the first section. In some embodiments, the first section is selected over the second section as the source section. For instance, a third fill pattern is generated for the second section based at least on the second structure. The third fill pattern includes at least one third fill structure in the second section. A first region of interest is identified in the first section. A second region of interest is identified in the second section. The first region of interest may be a mirror image of the second region of interest across the line 215. A quality of the first fill structures in the first region of interest is compared with a corresponding quality of the third fill structures in the second region of interest. The first section is selected over the second section based on a determination that the quality of the first fill structures in the first region of interest is better than the quality of the third fill structures in the second region of interest. The quality may be distance(s) of the fill structures to the first or second object, coupling (e.g., electrical, mechanical, magnetic, or thermal coupling) between fill structures and the first or second object, mechanical stress exerted by the fill structures on the first or second object, size(s) of the fill structures, other types of qualities, or some combination thereof.
The method 1300 also includes generating 1350 a second fill pattern based on the first fill pattern. In some embodiments, the second fill pattern is generated by performing a transformation, e.g., a reflection transformation across the line, on the first fill pattern. The second fill pattern is a mirror image of the first fill pattern across the line and comprises at least one second fill structure in the second section. The first fill pattern and the second fill pattern represent patterns of fill structures to be included in the IC device.
In some embodiments, the first section has a same dimension or size as the second section. In other embodiments, it is determined that the second section has a smaller size than the first section. Based on such a determination, a third section is generated by adding a fourth section to the second section so that the third section has the same size as the first section. The first fill pattern is transformed to a third fill pattern for the third section. A portion of the third fill pattern (e.g., the fill structures in the fourth section) is removed to form the second fill pattern.
In some embodiments, multiple lines are defined in the image. For instance, a different line is defined, e.g., based on the first object and the second object, so that the image includes a third section and a fourth section. At least a portion of the first object is in the third section. At least a portion of the second object is in the fourth section. Then a third fill pattern is generated. The third fill pattern includes a third fill structure in the third section. Also, a fourth fill pattern is generated by transforming the third fill pattern. The fourth fill pattern can be a mirror image of the third fill pattern across the different line. The fourth fill pattern comprises a fourth fill structure in the fourth section.
The method 1400 includes detecting 1410 a first object and a second object in an image. The image represents the IC device. The first object represents a first device in the IC device. The second object represents a second device in the IC device. The image may be two-dimensional or three-dimensional. In some embodiments, the image is a virtual representation of the IC device that is generated by a computing device. The image can include other objects that represent other components of the IC devices, such as other devices, a support structure associated with one or more devices in the IC device, layers in the IC device, etc.
A device (e.g., the first device or the second device) can be a functional component of the IC device. A device may perform an electronic function in the IC device. In some embodiments, a device is an electronic component, such as a transistor, capacitor, resistor, power rail, wire, bus, and so on. In other embodiments, a device includes a collection of multiple electronic components, such as an amplifier, oscillator, timer, microprocessor, memory, and so on.
The method 1400 further includes generates 1420 a fill pattern in the image. The fill pattern represents a pattern of fill structures to be included in the IC device. The fill structures, after included in the IC device, may surround at least a portion of the first object and at least a portion of the second object. A fill structure may be a non-function structure that is included in the IC device to facilitate fabrication of the IC device. The fill structures may have various shapes, sizes, or materials.
The method 1400 further includes simulating 1430 an electrical or mechanical impact of the fill structures on the first device or the second device, e.g., by performing an electrical or mechanical simulation based on the image. In an example, a first mechanical stress applied by at least some of the fill structures on the first device is simulated. Also, a second mechanical stress applied by at least some of the fill structures on the second device is simulated. Further, it is determined whether the first mechanical stress matches (e.g., equals, or substantially similar) the second mechanical stress. In another example, a first capacitance between the first device and a third device is simulated. And a second capacitance between the second device and the third device is simulated. Then it is determined whether the first capacitance matches (e.g., equals, or substantially similar) the second capacitance. Alternative to or in additional to simulating the electrical or mechanical impact, it is determined whether fill structures around the first device or the second device has a symmetric layout.
The method 1400 further includes identifying 1440 a region in the image based on the electrical or mechanical impact. In some embodiments, the region is a region that meets a boundary condition. The boundary condition may be mechanical, electrical, or structural. The method 1400 also includes modifying 1450 a portion of the fill pattern to generate a modified fill pattern in the image. The portion is in the region. The modified fill pattern represents a pattern of modified fill patterns to be included in the IC device. A simulated electrical or mechanical impact of the modified fill pattern on the first device or the second device is less than the electrical or mechanical impact of the fill pattern on the first device or the second device.
In some embodiments, multiple regions are identified and each region may be identified based on a different boundary condition. In such embodiments, the modification for addressing a region, even though improves the boundary condition of the region, may make the boundary condition of a different region worse. For situations like this, each boundary condition may be assigned a weight. The weight may also be a weight of the corresponding region. Each region is modified separately. Then the whole fill pattern is optimized based on the weights of the boundary conditions. For instance, a boundary condition having a higher weight is given a higher priority in the optimization process.
In some embodiments, the modification is performed on one layer of the IC device. In other embodiments, the modification is performed on multiple layers of the IC devices. For instance, another fill pattern on a different layer (e.g., a layer over the first object, the second object, and the fill pattern) is located can be modified to reduce the electrical or mechanical impact of the fill pattern on the first object or the second object.
As shown in
The package substrate 2252 may include conductive contacts 2263 that are coupled to conductive pathways 2262 through the package substrate 2252, allowing circuitry within the dies 2256 and/or the interposer 2257 to electrically couple to various ones of the conductive contacts 2264 (or to other devices included in the package substrate 2252, not shown).
The IC package 2200 may include an interposer 2257 coupled to the package substrate 2252 via conductive contacts 2261 of the interposer 2257, first-level interconnects 2265, and the conductive contacts 2263 of the package substrate 2252. The first-level interconnects 2265 illustrated in
The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254 of the dies 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive pathways (not shown) through the interposer 2257, allowing circuitry within the dies 2256 to electrically couple to various ones of the conductive contacts 2261 (or to other devices included in the interposer 2257, not shown). The first-level interconnects 2258 illustrated in
In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first-level interconnects 2265, and a mold compound 2268 may be disposed around the dies 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the mold compound 2268. Example materials that may be used for the underfill material 2266 and the mold compound 2268 are epoxy mold materials, as suitable. Second-level interconnects 2270 may be coupled to the conductive contacts 2264. The second-level interconnects 2270 illustrated in
The dies 2256 may take the form of any of the embodiments of the die 2002 discussed herein and may include any of the embodiments of an IC device having fill structures. In embodiments in which the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package. Importantly, even in such embodiments of a multi-chip package (MCP) implementation of the IC package 2200, fill structures may be provided in a single chip, in accordance with any of the embodiments described herein. The dies 2256 may include circuitry to perform any desired functionality. For example, one or more of the dies 2256 may be ESD protection dies, including fill structures as described herein, one or more of the dies 2256 may be logic dies (e.g., silicon-based dies), one or more of the dies 2256 may be memory dies (e.g., high bandwidth memory), etc. In some embodiments, any of the dies 2256 may include fill structures, e.g., as discussed above; in some embodiments, at least some of the dies 2256 may not include any III-N diodes with n-doped wells and capping layers.
The IC package 2200 illustrated in
In some embodiments, the circuit board 2302 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2302. In other embodiments, the circuit board 2302 may be a non-PCB substrate.
The IC device assembly 2300 illustrated in
The package-on-interposer structure 2336 may include an IC package 2320 coupled to an interposer 2304 by coupling components 2318. The coupling components 2318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2316. The IC package 2320 may be or include, for example, a die (the die 2002 of
The interposer 2304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to TSVs 2306. The interposer 2304 may further include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD protection devices, and memory devices. More complex devices such as further RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2304. In some embodiments, the IC devices implementing fill structures as described herein may also be implemented in/on the interposer 2304. The package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 2300 may include an IC package 2324 coupled to the first face 2340 of the circuit board 2302 by coupling components 2322. The coupling components 2322 may take the form of any of the embodiments discussed above with reference to the coupling components 2316, and the IC package 2324 may take the form of any of the embodiments discussed above with reference to the IC package 2320.
The IC device assembly 2300 illustrated in
A number of components are illustrated in
Additionally, in various embodiments, the computing device 2400 may not include one or more of the components illustrated in
The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2402 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which may itself include one or more memory devices such as volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and/or a hard drive. In some embodiments, the memory 2404 may include memory that shares a die with the processing device 2402. This memory may be used as cache memory and may include, e.g., eDRAM, and/or spin transfer torque magnetic random-access memory (STT-MRAM).
In some embodiments, the memory 2404 includes one or more non-transitory computer-readable media storing instructions executable to perform operations for providing fill patterns for IC devices, e.g., the method 1300 described above in conjunction with
In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, the communication chip 2412 may be configured for managing wireless communications for the transfer of data to and from the computing device 2400. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 2412 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 2412 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2412 may operate in accordance with other wireless protocols in other embodiments. The computing device 2400 may include an antenna 2422 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 2412 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2412 may include multiple communication chips. For instance, a first communication chip 2412 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2412 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2412 may be dedicated to wireless communications, and a second communication chip 2412 may be dedicated to wired communications.
In various embodiments, IC devices having fill structures as described herein may be particularly advantageous for use as part of ESD circuits protecting power amplifiers, low-noise amplifiers, filters (including arrays of filters and filter banks), switches, or other active components. In some embodiments, IC devices having one or more BPRs as described herein may be used in PMICs, e.g., as a rectifying diode for large currents. In some embodiments, IC devices having fill structures as described herein may be used in audio devices and/or in various input/output devices.
The computing device 2400 may include battery/power circuitry 2414. The battery/power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., AC line power).
The computing device 2400 may include a display device 2406 (or corresponding interface circuitry, as discussed above). The display device 2406 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
The computing device 2400 may include an audio output device 2408 (or corresponding interface circuitry, as discussed above). The audio output device 2408 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry, as discussed above). The audio input device 2418 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry, as discussed above). The GPS device 2416 may be in communication with a satellite-based system and may receive a location of the computing device 2400, as known in the art.
The computing device 2400 may include an other output device 2410 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The computing device 2400 may include an other input device 2420 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.
Example 1 provides a computer-implemented method for providing a fill pattern for an IC device, the method including: detecting a first object and a second object in an image that represents the IC device, where the first object represents a first device in the IC device, and the second object represents a second device in the IC device; defining a line in the image based on the first object and the second object so that the image includes a first section that is on a first side of the line and a second section that is on a second side of the line, where the first object is at least partially located in the first section, and the second object is at least partially located in the second section; generating a first structure based on the first object; generating a second structure based on the second object, where the second structure is a mirror image of the first structure across the line; generating a first fill pattern for the first section based on the first structure, the first fill pattern including a first fill structure in the first section; and generating a second fill pattern based on the first fill pattern, the second fill pattern being a mirror image of the first fill pattern across the line and including a second fill structure in the second section, where the first fill pattern and the second fill pattern represent patterns of fill structures to be included in the IC device.
Example 2 provides the computer-implemented method according to example 1, where the first structure or the second structure has a shape that combines a shape of the first object and a shape of the second object.
Example 3 provides the computer-implemented method according to example 1 or 2, where the first structure has a shape that is substantially identical to a shape of the first object or the second object.
Example 4 provides the computer-implemented method according to any of the preceding examples, where, prior to generating the second fill pattern based on the first fill pattern, the computer-implemented method further includes: generating a third fill pattern for the second section based on the second structure, the third fill pattern including a third fill structure in the second section, determining that a distance from the first fill structure to the first object is longer than a distance from the third fill structure to the second object, and selecting the first fill pattern over the third fill pattern.
Example 5 provides the computer-implemented method according to any of the preceding examples, further including: defining a different line based on the first object and the second object so that the image includes a third section on a first side of the different line and a fourth section that is on a second side of the different line, where the first object at least partially located in the third section, and the second object is at least partially located in the fourth section; generating a third fill pattern including a third fill structure in the third section; and generating a fourth fill pattern including a fourth fill structure in the fourth section, where the fourth fill pattern is a mirror image of the third fill pattern across the different line.
Example 6 provides the computer-implemented method according to any of the preceding examples, where the first fill pattern is substantially identical to the second fill pattern.
Example 7 provides the computer-implemented method according to any of the preceding examples, where defining the line in the image includes: identifying a symmetry axis or a symmetry point of the IC device, where the line is the symmetry axis, or the line crosses the symmetry point.
Example 8 provides a computer-implemented method for providing a fill pattern for an IC object, the method including: detecting a first object and a second object in an image that represents the IC device, where the first object represents a first device in the IC device, and the second object represents a second device in the IC device; generating a fill pattern in the image, the fill pattern representing a pattern of fill structures to be included in the IC device; simulating an electrical or mechanical impact of the fill structures on the first device or the second device based on the image; identify a region in the image based on the electrical or mechanical impact; and modifying a portion of the fill pattern to generate a modified fill pattern in the image, where: the portion is in the region, the modified fill pattern represents a pattern of modified fill structures to be included in the IC device, and a simulated electrical or mechanical impact of the modified fill structures on the first device or the second device is less than the electrical or mechanical impact of the fill structures on the first device or the second device.
Example 9 provides the computer-implemented method according to example 8, where simulating the electrical or mechanical impact of the fill structures on the first device or the second device includes: simulating a first mechanical stress applied by at least some of the fill structures on the first device; simulating a second mechanical stress applied by at least some of the fill structures on the second device; and determine whether the first mechanical stress matches the second mechanical stress.
Example 10 provides the computer-implemented method according to example 8 or 9, where simulating the electrical or mechanical impact of the fill structures on the first device or the second device includes: simulating a first capacitance between the first device and a third device in the IC device; simulating a second capacitance between the second device and the third device in the IC device; and determining whether the first capacitance matches the second capacitance.
Example 11 provides an IC device, including: a first fill pattern including first fill structures; a second fill pattern including second fill structures, where the second fill pattern a mirror image of the first fill pattern across a line in the IC device; a first device, at least partially surrounded by the first fill structures and at least partially located at a first side of the line; a second device, at least partially surrounded by the second fill structures and at least partially located at a second side of the line, where the second side is opposite the first side.
Example 12 provides the IC device according to example 11, further including a fill structure, a portion of which is located on the line.
Example 13 provides the IC device according to example 11 or 12, where the fill structure has a line symmetry across the line.
Example 14 provides the IC device according to any one of examples 11-13, where an individual first fill structure or an individual second fill structure includes a metal that is not connected to any of a signal source, a power source, or a reference potential during operation of the IC device.
Example 15 provides the IC device according to any one of examples 11-14, where a portion of the first device is a mirror image of a portion of the second device across the line.
Example 16 provides the IC device according to any one of examples 11-15, where a first portion of the first device is a mirror image of a second portion of the first device across the line.
Example 17 provides the IC device according to any one of examples 11-16, further including: a third fill pattern including third fill structures; and a fourth fill pattern including fourth fill structures, where: the third fill pattern is a mirror image of the fourth fill pattern across a different line in the IC device, the first device is at least partially surrounded by the third fill structures, and the second device is at least partially surrounded by the fourth fill structures.
Example 18 provides the IC device according to any one of examples 11-17, further including: a first layer including the first device, the second device, the first fill pattern, and the second fill pattern; and a second layer over the first layer, the second layer including a third fill pattern and a fourth fill pattern, where the third fill pattern is a mirror image of the fourth fill pattern across an additional line in the second layer, where the additional line is over the line.
Example 19 provides the IC device according to any one of examples 11-18, further including: a first layer including the first device, the second device, the first fill pattern, and the second fill pattern; and a second layer over the first layer, the second layer including a fill structure over the first device or the second device.
Example 20 provides the IC device according to any one of examples 11-19, where the first fill pattern is substantially identical to the second fill pattern.
Example 21 provides an IC package, including the IC device according to any one of examples 11-20; and a further IC component, coupled to the IC device.
Example 22 provides the IC package according to example 21, where the further IC component includes one of a package substrate, an interposer, or a further IC die.
Example 23 provides the IC package according to example 21 or 22, where the IC device according to any one of examples 11-20 may include, or be a part of, at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communications device.
Example 24 provides an electronic device, including a carrier substrate; and one or more of the IC devices according to any one of examples 11-20 and the IC package according to any one of examples 21-23, coupled to the carrier substrate.
Example 25 provides the electronic device according to example 24, where the carrier substrate is a motherboard.
Example 26 provides the electronic device according to example 24, where the carrier substrate is a PCB.
Example 27 provides the electronic device according to any one of examples 24-26, where the electronic device is a wearable electronic device or handheld electronic device.
Example 28 provides the electronic device according to any one of examples 24-27, where the electronic device further includes one or more communication chips and an antenna.
Example 29 provides the electronic device according to any one of examples 24-28, where the electronic device is an RF transceiver.
Example 30 provides the electronic device according to any one of examples 24-28, where the electronic device is one of a switch, a power amplifier, a low-noise amplifier, a filter, a filter bank, a duplexer, an upconverter, or a downconverter of an RF communications device, e.g., of an RF transceiver.
Example 31 provides the electronic device according to any one of examples 24-30, where the electronic device is a computing device.
Example 32 provides the electronic device according to any one of examples 24-31, where the electronic device is included in a base station of a wireless communication system.
Example 33 provides the electronic device according to any one of examples 24-31, where the electronic device is included in a user equipment device of a wireless communication system.
Example 34 provides the method according to any one of examples 1-10, further including processes for forming the IC device according to any one of claims 11-20.
Example 35 provides the method according to any one of examples 1-10, further including processes for forming the IC package according to any one of the claims 21-23.
Example 36 provides the method according to any one of examples 1-10, further including processes for forming the electronic device according to any one of the claims 24-31.
The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description.
