Patent Application
20190065431
The technology of the disclosure relates generally to a SOUNDWIRE audio bus, and, in particular, to frame synchronization for audio buses employing a SOUNDWIRE Extension protocol, such as SOUNDWIRE-XL or SOUNDWIRE-NEXT.
Mobile terminals are become increasingly common in modern society, having evolved from large, clunky, relatively simple telephonic devices into small, full range, multimedia devices with vastly improved processing power. Early mobile terminals generally provided poor sound quality and little, if any, visual image capacity. However, as both the processing power for these mobile terminals and the range of multimedia options has increased, the quality of the possible audio experience has likewise increased. In particular, contemporaneous mobile terminals may include multiple speakers, multiple microphones and, optionally, may communicate with remote audio devices such as headsets.
The MIPI® Alliance introduced the Serial Low Power Inter-chip Media Bus (SLIMbus®) protocol to help standardize communications among audio elements of a mobile terminal. SLIMbus has proved effective at providing communications among audio elements of a mobile terminal, but nevertheless has not seen widespread acceptance by the industry. Accordingly, to provide an alternative or supplement to the SLIMbus protocol, the MIPI Alliance has introduced the SOUNDWIRE specification. The SOUNDWIRE specification provides for a two-wire physical communications bus up to fifty centimeters in length, which is sufficient to house the audio elements within the mobile terminal. However, such distances may be too short for some regularly used ancillary devices, such as a headset. The MIPI Alliance thus has proposed a SOUNDWIRE Extension specification (“SOUNDWIRE Extension”), initially designated as SOUNDWIRE-XL, to enable communications over greater distances. Subsequent to this date, the MIPI Alliance changed the designation of the SOUNDWIRE Extension specification from SOUNDWIRE-XL to SOUNDWIRE-NEXT. It should be appreciated that such nomenclature may be subject to further renaming. At the time of this writing, the SOUNDWIRE Extension specification is at version 0.1 revision 1, published Jun. 8, 2016.
Implementations of the SOUNDWIRE-XL iteration of the SOUNDWIRE Extension specification employed a differential bi-directional clock-embedded physical link bus to transmit a bitstream between a downstream-facing interface (DFI) device (e.g., a master device) and one or more upstream-facing interfaces (UFIs) device (e.g., slave devices). The bitstream can be conceptualized as bitslots arranged horizontally in a row, with successive rows arranged vertically so that repeating features of the bitstream (e.g., synchronization strobe bits and data bits) are visible in columns of bitslots. The DFI inserts synchronization strobe bits into the bitstream for use by the UFI(s) in reconstructing a clock using a phase-locked loop (PLL) or a delay locked loop (DLL), and also provides frame synchronization patterns to enable frame synchronization by the UFI(s). However, each of the frame synchronization patterns conventionally occupies an entire bitslot within each row of the bitstream. Because rows may comprise as few as eight (8) or sixteen bitslots in some aspects, the frame synchronization patterns consequently may consume a relatively large portion of available transport bandwidth. This issue remains present in the current SOUNDWIRE-NEXT iteration of the SOUNDWIRE Extension specification.
Aspects disclosed in the detailed description include providing zero-overhead frame synchronization using synchronization strobe polarity for SOUNDWIRE Extension buses. In this regard, in one aspect, a processor-based downstream-facing interface (DFI) device (also referred to as a “master device” or “master”) is configured to determine a polarity of a next synchronization strobe of a bitstream based on a value of a next frame synchronization pattern. The processor-based DFI device adjusts the next synchronization strobe of the bitstream to comprise a signal transition corresponding to the polarity. In some aspects, a low-to-high signal transition may correspond to a frame synchronization pattern value of zero (0) and a high-to-low signal transition may correspond to a frame synchronization pattern of one (1), while some aspects may interpret a low-to-high signal transition as corresponding to a frame synchronization pattern value of one (1) and a high-to-low signal transition as corresponding to a frame synchronization pattern of zero (0). The processor-based DFI device then transmits the bitstream containing the next synchronization strobe (e.g., via a SOUNDWIRE Extension bus to one or more upstream-facing interface (UFI) devices, also referred to as a “slave device” or “slave”). In another aspect, a processor-based UFI device receives the bitstream, and detects the encoded polarity of the synchronization strobe. The processor-based UFI device reconstructs the frame synchronization pattern based on the polarity of the synchronization strobe, and performs frame synchronization based on the frame synchronization pattern.
In another aspect, a processor-based DFI device is provided. The processor-based DFI device comprises an application processor that comprises a control circuit and a bus interface, and that is communicatively coupled to a bus. The application processor is configured to determine, by the control circuit of the application processor, a polarity of a next synchronization strobe of a bitstream based on a value of a next frame synchronization pattern. The application processor is further configured to adjust the next synchronization strobe of the bitstream to comprise a signal transition corresponding to the polarity. The application processor is also configured to transmit the bitstream containing the next synchronization strobe via the bus.
In another aspect, a method for encoding frame synchronization patterns is provided. The method comprises determining, by a DFI device, a polarity of a next synchronization strobe of a bitstream based on a value of a next frame synchronization pattern. The method further comprises adjusting the next synchronization strobe of the bitstream to comprise a signal transition corresponding to the polarity. The method also comprises transmitting the bitstream containing the next synchronization strobe via a bus.
In another aspect, a processor-based UFI device is provided. The processor-based UFI device comprises an application processor that comprises a control circuit and a bus interface, and that is communicatively coupled to a bus. The application processor is configured to receive, by the control circuit of the application processor, a bitstream comprising a synchronization strobe via the bus. The application processor is further configured to detect a polarity of the synchronization strobe indicated by a signal transition of the synchronization strobe. The application processor is also configured to reconstruct a frame synchronization pattern based on the polarity of the synchronization strobe. The application processor is additionally configured to perform frame synchronization based on the frame synchronization pattern.
In another aspect, a method for decoding frame synchronization patterns is provided. The method comprises receiving, by a processor-based UFI device, a bitstream comprising a synchronization strobe via a bus. The method further comprises detecting a polarity of the synchronization strobe indicated by a signal transition of the synchronization strobe. The method also comprises reconstructing a frame synchronization pattern based on the polarity of the synchronization strobe. The method additionally comprises performing frame synchronization based on the frame synchronization pattern.
With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
Aspects disclosed in the detailed description include providing zero-overhead frame synchronization using synchronization strobe polarity for SOUNDWIRE Extension buses. In this regard, in one aspect, a processor-based downstream-facing interface (DFI) device (also referred to as a “master device” or “master”) is configured to determine a polarity of a next synchronization strobe of a bitstream based on a value of a next frame synchronization pattern. The processor-based DFI device adjusts the next synchronization strobe of the bitstream to comprise a signal transition corresponding to the polarity. In some aspects, a low-to-high signal transition may correspond to a frame synchronization pattern value of zero (0) and a high-to-low signal transition may correspond to a frame synchronization pattern of one (1), while some aspects may interpret a low-to-high signal transition as corresponding to a frame synchronization pattern value of one (1) and a high-to-low signal transition as corresponding to a frame synchronization pattern of zero (0). The processor-based DFI device then transmits the bitstream containing the next synchronization strobe (e.g., via a SOUNDWIRE Extension bus to one or more upstream-facing interface (UFI) devices, also referred to as a “slave device” or “slave”). In another aspect, a processor-based UFI device receives the bitstream, and detects the encoded polarity of the synchronization strobe. The processor-based UFI device reconstructs the frame synchronization pattern based on the polarity of the synchronization strobe, and performs frame synchronization based on the frame synchronization pattern.
Before describing how synchronization strobe polarity is used for zero-overhead frame synchronization, elements of a conventional SOUNDWIRE Extension system, as well as the operations of and interactions between a conventional SOUNDWIRE Extension downstream-facing interface (DFI) device and a conventional upstream-facing interface (UFI) device, are first discussed. It should be appreciated that, during preparation of the incorporated parent provisional application, the designation for the SOUNDWIRE Extension specification was SOUNDWIRE-XL. As noted above, the designation has since migrated to SOUNDWIRE-NEXT, although the relevant portions of the specifications are identical. For the sake of clarity, the term “SOUNDWIRE Extension” is used herein to refer to the SOUNDWIRE-XL and SOUNDWIRE-NEXT specifications containing the relevant portions referenced herein, as well as to future iterations of the specification that also include the relevant portions referenced herein. In this regard,
Referring now to
The SOUNDWIRE sub-system 110 may include a plurality of microphones 112(1)-112(2) and a plurality of speakers 114(1)-114(2) (as well as any other audio components) comprising slave devices within the SOUNDWIRE sub-system 110. In an exemplary aspect, the SOUNDWIRE sub-system 110 may be instantiated in a headset. The bridge 104 may include a control system that enables signal conversion between the long cable 106 and the SOUNDWIRE sub-system 110. The bridge 104 is coupled to the plurality of microphones 112(1)-112(2) and the plurality of speakers 114(1)-114(2) via a multi-wire bus 116 that is compliant with the SOUNDWIRE specification (i.e., a multi-wire bus, including a clock line and one or more data lines, and having a length less than 50 cm). In an exemplary aspect, the long cable 106 uses a SOUNDWIRE Extension protocol described below, and the bridge 104 converts messages in the SOUNDWIRE Extension protocol from the application processor 102 to a SOUNDWIRE protocol and converts messages in the SOUNDWIRE protocol from the SOUNDWIRE sub-system 110 to the SOUNDWIRE Extension protocol. It is to be understood that the application processor 102 may be a native SOUNDWIRE element, and may operate with the SOUNDWIRE Extension protocol through a protocol conversion using an internal bridge or may directly populate signals using the SOUNDWIRE Extension protocol.
To illustrate an exemplary SOUNDWIRE Extension bitstream employing conventional synchronization strobes and frame synchronization patterns,
While the bitstream 206 comprises a continuous signal through the physical medium, the bitstream 206 can be conceptualized as quantized symbols (i.e., synchronization strobes and data bits) and bitslots in which those symbols may be transmitted. Because the bitstream 206 contains features that are repeated at regular intervals, it may be represented visually as bitslots in a rectangular structure, wherein successive bitslots are shown horizontally within a row and successive rows are arranged vertically so that repeating features are visible in columns of bitslots. Accordingly, as seen in
The bitstream 206 is communicated between the processor-based DFI device 202 and the processor-based UFI device 204 via a differential bi-directional clock-embedded physical link bus (not shown). To enable the processor-based UFI device 204 to reconstruct a transport clock (e.g., having a frequency equal to or larger than the rate of the bitslots 210(0)-210(B), as a non-limiting example), the processor-based DFI device 202 inserts synchronization strobes, indicated by a transition between a synchronization bit 0 (e.g., synchronization (“SYNC 0”) bits 212(0), 214(0)) and a synchronization bit 1 (e.g., synchronization (“SYNC 1”) bits 212(1), 214(1)), at pre-determined positions. For the sake of clarity, the pairs of synchronization bits 212(0), 212(1) and 214(0), 214(1) may each be referred to herein as a “synchronization strobe.” In the example of
In the example of
However, one disadvantage of conventional bitstreams such as the bitstream 206 of
In this regard,
As seen in
Bitstreams encoded and transmitted by the processor-based DFI device 300 are relayed by a bridge 326, which corresponds in functionality to the bridge 104 of
To illustrate exemplary zero-overhead frame synchronization based on a polarity of a synchronization strobe as provided by the processor-based DFI device 300 and the processor-based UFI device 302 of
To illustrate exemplary operation of the processor-based UFI device 302 of
To provide a system-level block diagram of an exemplary device employing a SOUNDWIRE Extension bus,
With continued reference to
With continued reference to
With continued reference to
Providing zero-overhead frame synchronization using synchronization strobe polarity for SOUNDWIRE Extension buses according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.
In this regard,
Other master and slave devices can be connected to the system bus 808. As illustrated in
The CPU(s) 802 may also be configured to access the display controller(s) 820 over the system bus 808 to control information sent to one or more displays 826. The display controller(s) 820 sends information to the display(s) 826 to be displayed via one or more video processors 828, which process the information to be displayed into a format suitable for the display(s) 826. The display(s) 826 can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.
Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. The master devices, and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The present application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application Ser. No. 62/552,739 entitled “PROVIDING ZERO-OVERHEAD FRAME SYNCHRONIZATION USING SYNCHRONIZATION STROBE POLARITY FOR SOUNDWIRE-XL BUSES” and filed on Aug. 31, 2017, the contents of which is incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 62552739 | Aug 2017 | US |
