Patent Application
20090327382
(Related application): This application claims the benefit of priority of Japanese Patent Application No. 2006-201796 (application of Jul. 25, 2006), the content of which is incorporated herein in its entirety by reference thereto.
The present invention relates to a pseudorandom number generation device, a stream encryption device, and a program, and in particular, to what is called a clock control type of pseudorandom number generation device, stream encryption device, and program, in which a plurality of linear feedback registers (referred to below as LFSRs) are used, and LFSR operation control is performed according to an internal state thereof, to generate random numbers.
As data digitization of information progresses, encryption for implementing protection of information and confidential communication is becoming an essential technology. The encryption is broadly classified, based on encryption method used, into common key encryption (termed herein “symmetric key encryption”) and public key encryption. The former symmetric key encryption is an encryption method which uses the same symmetric key, with regard to encryption and decryption, and the key is privately (secretly) stored. The other public key encryption has different keys for encryption and decryption, and one key of either thereof can be made public. In general, the symmetric key encryption is high speed and thus is used in communication of large quantities of data; and the public key encryption is low speed but key management is easy and thus the public key encryption is used in key distribution, signatures, and authentication for symmetric key encryption.
The symmetric key encryption can be classified, based on its configuration, into block encryption and stream encryption. The block encryption is a method in which encryption is performed by transpositions and operations on data divided into block units, while the stream encryption performs sequential encryption for each of prescribed output units (for example, 1 to several bits), using pseudo-random numbers outputted by a pseudorandom number generator. Among stream encryptions, A5/1 may be cited as a representative algorithm of a clock control method in which LFSRs are made to operate non-continuously.
The A5/1 is an operation control algorithm with 3 LFSR component elements. In general the LFSRs are used as generators of pseudo-random numbers, but since mathematical analysis can be easily done, usage as is, for encryption, is not possible. Consequently, in A5/1, by combining a plurality of LFSRs, and in addition by non-continuously controlling operation of the LFSRs, estimation of an internal state at a certain time is made difficult, and strength is provided for encryption. There are many proposals, outside of the A5/1, of stream encryption provided with this type of plurality of LFSRs and an operation controller which performs clock control thereof.
However, to improve safety of encryption, private information, such as a key and the like, must be not capable of being easily estimated. Cryptanalysis methods such as linear cryptanalysis, differential cryptanalysis and the like, which perform mathematical cryptanalysis or exhaustive search for the key, are known, but it can be said that analysis within a realistic time is not possible.
On the other hand, assuming that an attacker is capable of precisely measuring processing time or power consumption, as with IC cards or mobile terminals with encryption functions, side channel attacks which attempt to obtain private information from information thereof, and strategies against these have become a large research theme.
As specific methods of attack among the abovementioned side channel attacks, timing attacks focusing on processing time (refer to Non-Patent Document 1), and power analysis attacks focusing on power consumption are known.
Power analysis attacks include Simple Power Analysis (SPA) and Differential Power Analysis (DPA) (refer to Non-Patent Document 2). Furthermore, this document describes a specific method of attack with regard to DPA against a DES which is a known block encryption.
Furthermore, Patent Document 1 discloses a symmetric key block encryption device in which, aside from handling of vulnerabilities with respect to power analysis attacks to the above described block encryption, and a regular round function unit into which the plain text data is inputted, avoiding making a processing algorithm more complex, a dummy round function unit that executes dummy operations is provided, and attack resistance is increased by making power analysis more difficult.
The entire disclosures of the abovementioned Patent Document 1 and Non-Patent Documents 1 and 2 are incorporated herein by reference thereto.
The inventor of the present invention has found a very effective method of attack against a stream encryption method that uses a clock control type of pseudo-random number generator represented by the above described A5/1. First, this attack method is described.
To simplify the description, consideration is given to cases in which an attempt is made to analyze a stream encryption system operating by clock control similar to the A5/1 algorithm configured from 3 LFSRs shown in
Here, each LFSR 831 to 833 may have an arbitrary bit length. Furthermore, the operation controller 9 performs majority decisions with respect to arbitrary bit register values of each LFSR, and operates a majority LFSR. In the abovementioned operation controller 9, an arbitrary register (C1 to C3 in
In searching internal states of each of the LFSRs 831 to 833, with the clocking tap as a node, a tree search is used in which the number of branches is determined from the number of moves of time t−1 to time t. The tree search uses depth first search; when a certain depth is reached a consistency check with output is performed; and in cases in which an inconsistency is confirmed, search of that branch is stopped, and search of a next branch is performed. The search is performed until internal states of all the LFSRs are determined.
Here, a description is given concerning a method of determining the number of moves described above.
On the other hand, when the pseudo-random number generator that operates by the A5/1 algorithm is configured by LSI or FPGA hardware or the like, all processing is executed at approximately the same time. However, in such case also, from the fact that the number of LFSRs operating at the same time changes, by differences in the number of moves, a difference occurs in power consumption quantity in one output generation processing operation (one output unit). Therefore, in cases of hardware implementation also, it is possible to determine the number of moves using the size of the above described power consumption quantity.
As described above, the stream encryption method, configured from N LFSRs exemplified in
The present invention has been made in view of vulnerability of the clock control type pseudo-random number generator as described above, and has as an object the provision of a pseudorandom number generation device, a stream encryption device, and a program, having resistance to the attack method proposed by the present inventor.
According to a first aspect of the present invention, there are provided: a pseudo-random number generation device of a clock control type that has N LFSRs and performs operational control of each of the LFSRs according to an internal state of each of the LFSRs, to generate a pseudo-random number, characterized by comprising: means for making uniform generation processing time of one output unit, irrespective of the number of operations of the LFSRs;
a stream encryption device which uses the pseudo-random number outputted from the pseudo-random number generation device to perform encryption-decryption processing; and
a program for realization thereof.
According to a second aspect of the present invention, there are provided: a pseudo-random number generation device of a clock control type that has N LFSRs and performs operational control of each of the LFSRs according to an internal state of each of the LFSRs, to generate a pseudo-random number, characterized by comprising: means for varying generation processing time of one output unit, with a variation range larger than processing time necessary for at least one operation of an LFSR;
a stream encryption device which uses the pseudo-random number outputted from the pseudo-random number generation device to perform encryption-decryption processing; and
a program for realization thereof.
According to a third aspect of the present invention, there are provided: a pseudo-random number generation device of a clock control type that has N LFSRs and performs operational control of each of the LFSRs according to an internal state of each of the LFSRs, to generate a pseudo-random number, characterized by comprising: means for making constant power consumed in generation processing of one output unit;
a stream encryption device which uses the pseudo-random number outputted from the pseudo-random number generation device to perform encryption-decryption processing; and
a program for realization thereof.
According to a fourth aspect of the present invention, there are provided: a pseudo-random number generation device of a clock control type that has N LFSRs and performs operational control of each of the LFSRs according to an internal state of each of the LFSRs, to generate a pseudo-random number, characterized by comprising: means for varying power consumed in generation processing of one output unit, with a variation range larger than power consumption necessary for at least one operation of an LFSR;
a stream encryption device which uses the pseudo-random number outputted from the pseudo-random number generation device to perform encryption-decryption processing; and
a program for realization thereof.
According to the present invention since it is possible to conceal the number of operations of a LFSR required to generate one output unit, it is possible to obtain an encryption system in which resistance against an attack method proposed by the present inventor is improved.
Next, preferred modes for carrying out the invention will be described, making reference to the drawings.
The data storage unit 31 of the storage device 3 is a location at which various parameters necessary for program execution are stored, and an encrypted private key 311 is stored here. The program storage unit 32 is a location at which various programs necessary for the encryption-decryption processing device are stored, and an encryption program (stream encryption program) 321 for implementing processing means of each exemplary embodiment, described later, is stored here.
The abovementioned encryption-decryption processing device can be realized by various types of information processing device, such a personal computer (PC), mobile terminal, IC card, reader-writer, and the like, by installing software or hardware as described later. For example, in cases in which the encryption-decryption processing device is realized by a personal computer (PC), by reading the encryption program 321 stored in a supplementary storage device such as a magnetic disk or the like, not shown in the drawings, to the storage device 3, execution by the arithmetic processing unit 1 is possible.
Next, a first exemplary embodiment of the present invention will be described, in which, by making uniform processing time required for one output generation processing operation (one output unit) in a process of generating a pseudo-random number, the number of LFSR operations (number of moves) for one output is concealed.
The delay (processing) means 811 to 81N are means which, with regard to the LFSRs 801 to 80N for which selection of shift processing, by the operation controller 9, was not performed, execute delay processing that consumes processing time approximately the same as shift processing of the LFSRs 801 to 80N.
An encryption-decryption processing unit 7 is a means for executing encryption or decryption of plain text 5 or encrypted text 6 using pseudo-random numbers outputted from the pseudo-random number generator 4.
Therefore, a point of difference from a conventional configuration shown in
Next, operation of the pseudo-random number generator 4 composed as described above will be described.
First, an encryption program 321 is started up by being called by another program (step A1), and first, initialization is performed as preparation for generating a pseudo-random number (step A2). In this initialization setting, agitation of internal data is performed by parameters of the private key and the like.
When the initialization of step A2 is completed, the operation controller 9 performs determination of operation for LFSR_1 (801 in
Here, when the operation of the LFSR_1 (801 in
On the other hand, in cases in which the operation of the LFSR_1 (801 in
In the same way, respective processing accompanying the abovementioned operation determination and a determination result is performed for LFSR_2 to N(802 to 80N in
After processing of all the LFSRs is completed, with internal states thereof as a basis, pseudo-random number generation processing of a prescribed output unit is performed (step A7).
A series of processing from step A3 to step A7 is repeatedly executed, and is completed at a point in time at which a pseudo-random number of a specified length is generated (steps A8 and A9).
As described above, according to the present exemplary embodiment, since in cases in which shift processing was not selected by the operation controller 9 also, delay processing of an approximately similar amount is necessarily carried out, a processing time of one operation is identical to a processing time when all LFSRs perform a shift operation, and is made uniform (constant). As a result, it is possible to make derivation of the private key by measuring the processing time from outside, difficult.
Moreover, using LFSRs of a size the same as the LFSRs 801 to 80N, as the delay means 811 to 81N, by performing shift control thereof by the operation controller 9, it is possible to realize the abovementioned delay processing. Furthermore, in addition, if processing is equivalent to shift processing time of each of the LFSRs 801 to 80N, it is possible to employ a means which executes delay processing such as Wait processing or the like.
In particular, in cases in which shift processing is executed by dummy LFSRs the same size as the former LFSRs, since not only the processing time but also commands executed by the arithmetic processing unit 1 are equivalent, an advantage of being stronger against power analysis deriving internal states from power consumption waveforms is also realized.
Next, in a method different from the abovementioned first exemplary embodiment, a second exemplary embodiment of the present invention will be described in which, by making uniform processing time required for one output generation processing operation (one output unit) in a process of generating a pseudo-random number, the number of LFSR operations (number of moves) is concealed.
The delay means 820 is a means which, with regard to the LFSRs 801 to 80N for which selection of shift processing, by the operation controller 9, has not been performed, executes delay processing that consumes processing time approximately the same as shift processing of the LFSRs 801 to 80N.
Therefore, a point of difference from the abovementioned first exemplary embodiment is that the delay means 820 is provided instead of the delay means 811 to 81N, similar in number N to the N LFSRs.
Next, operation of the pseudo-random number generator 4 composed as described above will be described.
Operations of the present exemplary embodiment shown in steps A1 to A6, A8, and A9 of
After all LFSR operation determinations and accompanying shift processing have been completed, the operation controller 9 performs a comparison as to whether the number stored in the counter is equal to a predetermined number of shift processing operations (for example, the number N of LFSRs) (step A12; delay processing operation determination).
In cases in which, in the abovementioned comparison result the number stored in the counter is less than the predetermined number of shift processing operations, the operation controller 9 implements delay processing by the delay means 820, while incrementing the number stored in the counter (step A13).
Processing of the abovementioned step A12 and step A13 is repeated until the number stored in the counter is equal to the predetermined number of shift processing operations.
In the present exemplary embodiment, a series of processing from step A3 to step A7 (including steps A12 and A13) is repeatedly executed, and is ended at a point in time at which a pseudo-random number of a specified length is generated (steps A8 and A9).
As described above, in the present exemplary embodiment also, since in cases in which shift processing has not been selected by the operation controller 9 also, delay processing of an approximately similar amount is necessarily carried out, processing time of one operation is made uniform (made constant). As a result, it is possible to make derivation of the private key by measuring the processing time from outside, difficult.
Of course, in cases in which bit widths of the respective LFSRs 801 to 80N are each different, it is desirable to have the operation controller 9 send relevant bit width information to the delay means 820, and make it operate such that a delay is generated that is approximately the same as for LFSRs that have not been selected for operation, and make uniform (make constant) overall processing time of one operation.
Furthermore, in the present exemplary embodiment, a LFSR is used as the delay means 820, and by performing shift control thereof by the operation controller 9, it is possible to realize the abovementioned delay processing. Moreover, in addition, if processing is equivalent to shift processing time of each of the LFSRs 801 to 80N, it is possible to employ a means which executes delay processing such as Wait processing or the like.
Furthermore, in cases in which pseudo shift processing is executed by the LFSR as the abovementioned delay processing, since not only the processing time but also commands executed by the arithmetic processing unit 1 are equivalent, an advantage of being stronger (more resistant) against power analysis deriving internal states from power consumption waveforms is also realized.
Next, a third exemplary embodiment of the present invention will be described, in which, by varying processing time required for one output generation processing operation (one output unit) in a process of generating a pseudo-random number, the number of LFSR operations (number of moves) is concealed.
The random delay means 11 is a means which executes random delay processing independently from internal states and behavior of the N LFSRs 801 to 80N. This type of delay processing can be implemented by, for example, processing executed by randomly selecting a plurality of operations having different processing times. As is clear from the object of concealing the number of LFSR operations (number of moves) as described above, variation range for each operation realized by this delay processing is larger than processing time necessary for at least one LFSR operation (shift processing).
Next, operation of the pseudo-random number generator 4 configured as described above will be described.
Operations of the present exemplary embodiment shown in steps A1 to A6, and A7 to A9 of
At a time point when step A6 ends, the operation controller 9 makes the random delay means 11 operate (step A14).
As described above, in the present exemplary embodiment, processing time of one operation of generating a pseudo-random number can be made non-uniform, and it is possible to make derivation of a private key by measuring processing time from outside, difficult.
In the abovementioned exemplary embodiment, a description has been given in which one random delay processing operation is performed after all shift processing has been completed, but since an object is to make non-uniform and conceal time required for generation of one output unit, of a pseudo-random number, there is no particular limitation to the number of operations of, and execution timing of, the random delay processing. That is, it is possible to make an insertion an arbitrary number of times at an arbitrary location in steps A1 to A6 of
In the abovementioned exemplary embodiment, a description has been given in which variation range of processing by the random delay processing is larger than processing time necessary for at least one LFSR operation (shift operation), but having a larger time variation, of course, enables derivation of actual processing time to be made difficult.
Next a fourth exemplary embodiment of the present invention will be described, in which, by making uniform (making constant) power consumption required for one output generation processing operation (one output unit) in a process of generating a pseudo-random number, the number of LFSR operations (number of moves) for one output is concealed.
An encryption-decryption processing unit 7 is a means for executing encryption or decryption of plain text 5 or encrypted text 6 using pseudo-random numbers outputted from the pseudo-random number generator 4.
The N LFSRs 801 to 80N perform shift operations based on an operation selection of the operation controller 9, perform agitation while repeating shift processing on private information given in advance of a private key or the like, and retain post-agitation data.
The dummy LFSRs 811 to 81N are an LFSR group that operates with an identical transition function and with an identical bit width as the LFSRs 801 to 80N, and perform a shift operation exclusively with the LFSRs 801 to 80N, that is when corresponding LFSRs are in a halted state.
As described above, according to the present exemplary embodiment it is possible to make uniform the power consumption required for each operation of generating a pseudo-random number, and even assuming that power consumption is measured from outside, estimation of the number of LFSR operations (number of moves) is difficult. Therefore, it is possible to make derivation of the private key by power analysis, difficult.
Moreover, in the abovementioned exemplary embodiment, a description has been given in which, in order to improve uniformity of the power consumption, the dummy LFSRs 811 to 81N operate with a similar transition function and with a similar bit width as the LFSRs 801 to 80N, but it is possible to add appropriate design changes within a range in which resistance to the abovementioned power analysis attack can be retained. For example, without being limited to the LFSRs, it is possible to employ shift registers that consume power of an approximately similar amount, or to employ LFSRs having arbitrary bit widths and transition functions.
Next, in a configuration different from the abovementioned fourth exemplary embodiment, a fifth exemplary embodiment of the present invention will be described in which, by making power consumption required for one output generation processing operation (one output unit) uniform (constant) in a process of generating a pseudo-random number, the number of LFSR operations (number of moves) is concealed.
Therefore, a point of difference from the abovementioned fourth exemplary embodiment is that instead of providing N dummy LFSRs, the dummy LFSRs 821 to 82M of M in number, which is less than N, are sufficient. The number M of the abovementioned dummy LFSRs can, for example in cases in which LFSRs that are operating are determined by a majority decision, be curtailed to less than half the total number of LFSRs.
The LFSRs 801 to 80N perform a shift operation based on operation selection of the operation controller 9, perform agitation (or mixing) while repeating shift processing on private information given in advance such as a private key or the like, and retain post-agitation data.
In cases in which the LFSRs 801 to 80N have not been selected for operation by control of the operation controller 9, the dummy LFSRs 821 to 82M perform shift operations.
As described above, the dummy LFSRs are made to operate, the same as the LFSRs in which shift processing has not been performed, and it is possible to make uniform power consumption required for one operation of generating a pseudo-random number. Therefore, in the present exemplary embodiment also, estimation of the number of LFSR operations (number of moves) is difficult, and derivation of the private key by power analysis is made difficult.
From a viewpoint of increasing uniformity of power consumption, it may be said that it is desirable that the dummy LFSRs 821 to 81M that operate with an identical transition function and an identical bit width as the LFSRs 801 to 80N be provided and selectively operated. Furthermore, with regard to the dummy LFSRs 821 to 81M, without being limited to LFSRs, it is possible to employ shift registers that consume power of an approximately similar amount.
Next, a sixth exemplary embodiment of the present invention will be described, in which power consumption required for one output generation processing operation (one output unit) in a process of generating a pseudo-random number is varied, and the number of LFSR operations (number of moves) is concealed.
The N LFSRs 801 to 80N perform shift operations based on an operation selection of the operation controller 9, perform agitation while repeating shift processing on secret information given in advance of a secret key or the like, and retain post-agitation data.
The noise generation source 12 is a random noise generation source device that operates independently from (does not depend on) internal states and behavior of the N LFSRs 801 to 80N, and has variation of power that is larger than power consumed in shift processing of at least one LFSR.
As described above, in the present exemplary embodiment, power consumption of one operation of generating a pseudo-random number can be made non-uniform, and it is possible to make derivation of a secret key by measuring power consumption from outside, difficult.
In the abovementioned exemplary embodiment, a description has been given in which variation range of power produced by the noise generation source 12 is larger than the power consumption necessary for at least one LFSR operation (shift operation), but having a larger variation of power quantity, of course, enables derivation of actual LFSR power consumption to be made difficult.
A description has been given above concerning preferred exemplary embodiments of the present invention, but it is clearly possible to add various types of modification to the invention within a range that does not depart from the scope of the invention in which an attack method proposed by the present inventor is made ineffective by concealing the true number of LFSR operations.
For example, as shown in
Furthermore, as shown in
In addition, modifications and adjustments of embodiments and examples are possible within the bounds of the entire disclosure (including the scope of the claims) of the present invention, and also based on fundamental technological concepts thereof. Furthermore, a wide variety of combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention.
The present invention can be applied to all fields requiring an encryption system, but in view of characteristics of the abovementioned present invention, the invention can be preferably applied to devices that are required to be tamper resistant and to programs therefor.
Modifications and adjustments of exemplary embodiments and examples are possible within the bounds of the entire disclosure (including the scope of the claims) of the present invention, and also based on fundamental technological concepts thereof. Furthermore, a wide variety of combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-201796 | Jul 2006 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2007/064148 | 7/18/2007 | WO | 00 | 1/23/2009 |
