Patent Application
20250218325
This application claims the benefit of the Republic of Korea Patent Application No. 10-2023-0197122 filed on Dec. 29, 2023, which is hereby incorporated by reference in its entirety.
The present disclosure relates to a pseudo signal generator and a display apparatus including the same.
As information technology advances, the market for display apparatuses which are a connection medium between a user and information is growing. Therefore, the use of display apparatuses such as light emitting display apparatuses, quantum dot display (QDD) apparatuses, and liquid crystal display (LCD) apparatuses is increasing.
The display apparatuses described above include a display panel which includes a plurality of subpixels, a driver which outputs a driving signal for driving the display panel, and a power supply which generates power which is to be supplied to the display panel or the driver.
In such display apparatuses, when the driving signal (for example, a scan signal and a data signal) is supplied to each of the subpixels provided in the display panel, a selected subpixel may transmit light or may self-emit light, and thus, an image may be displayed.
The present disclosure may solve a problem of radiation mismatching caused by a load difference between a shift register and a pseudo pattern part, may increase robustness to noise, and may offset and minimize an electric field causing electromagnetic interference (EMI). Also, the present disclosure may a pseudo signal of a current type corresponding to clock signals and may summate at least one of the signals to decrease an area occupied by a pseudo pattern part and an integration pattern of the pseudo pattern part, thereby reducing a bezel region of a display panel.
To achieve these objects and other advantages and in accordance with the purpose of the disclosure, as embodied and broadly described herein, a display apparatus includes: a display panel configured to display an image; a shift register configured to output a gate signal which is to be applied to the display panel, based on a periodicity signal output from a level shifter; a pseudo generator configured to sense the periodicity signal to convert it into a current and invert a phase to output as a pseudo signal of an inverted current type; and a pseudo pattern part disposed on the display panel, the pseudo pattern part including a pattern where the pseudo signal is applied.
The pseudo pattern part may include a pattern for offsetting an electric field generated from the periodicity signal, based on the pseudo signal.
The pseudo generator may include: a current sensing circuit configured to sense the periodicity signal and a phase inverting circuit configured to invert a phase of a sensed current to output as the pseudo signal of the inverted current type.
The pseudo generator may include a current sensing and phase inverting circuit including a first transistor configured to sense the periodicity signal to convert it into a current and a second transistor configured to operate identical to the first transistor and invert a phase of a sensed current to output as the pseudo signal of the inverted current type.
The first transistor and the second transistor may be configured as a current mirror type.
The first transistor may include a first electrode connected to an input terminal, a second electrode connected to an output terminal, and a gate electrode connected to the output terminal and a gate electrode of the second transistor, and the second transistor may include a first electrode connected to the pseudo pattern part, a second electrode connected to a ground terminal, and the gate electrode connected to the output terminal and the gate electrode of the first transistor.
The pseudo generator may further include a current summation circuit configured to summate one or more inverted currents to generate a pseudo signal of a summation current type.
The pseudo generator and the pseudo pattern part may be disposed in a non-display area of the display panel.
The periodicity signal may include clock signals.
In another embodiment of the present disclosure, a pseudo signal generator includes: a pseudo generator configured to sense a periodicity signal to convert it into a current and invert a phase to output as a pseudo signal of an inverted current type; and a pseudo pattern part including a pattern for offsetting an electric field generated from the periodicity signal, based on the pseudo signal.
The pseudo generator may include a first transistor configured to sense the periodicity signal to convert it into a current and a second transistor configured to operate identical to the first transistor and invert a phase of a sensed current to output as the pseudo signal of the inverted current type.
The first transistor may include a first electrode connected to an input terminal, a second electrode connected to an output terminal, and a gate electrode connected to the output terminal and a gate electrode of the second transistor, and the second transistor may include a first electrode connected to the pseudo pattern part, a second electrode connected to a ground terminal, and the gate electrode connected to the output terminal and the gate electrode of the first transistor.
At least one of the pseudo generator and the pseudo pattern part may further include a current summation circuit configured to summate one or more inverted currents to generate a pseudo signal of a summation current type.
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the disclosure and together with the description serve to explain the principle of the disclosure. In the drawings:
Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are shown. The disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the disclosure to those skilled in the art.
A display apparatus according to the present disclosure may be applied to televisions (TVs), video players, personal computers (PCs), home theaters, electronic devices for vehicles, and smartphones, but is not limited thereto. The display apparatus according to the present disclosure may be implemented as a light emitting display apparatus, a quantum dot display (QDD) apparatus, or a liquid crystal display (LCD) apparatus. Hereinafter, for convenience of description, a light emitting display apparatus self-emitting light by using an inorganic light emitting diode or an organic light emitting diode will be described for example.
Moreover, a transistor described below may be implemented with an n-type transistor, a p-type transistor, or a combination of an n-type transistor and a p-type transistor. A transistor may be a three-electrode element including a gate, a source, and a drain. The source may be an electrode which provides a carrier to a transistor. In the transistor, a carrier may start to flow from the source. The drain may be an electrode where the carrier flows from the transistor to the outside. That is, in the transistor, the carrier flows from the source to the drain.
In the p-type transistor, because a carrier is a hole, a source voltage may be higher than a drain voltage so that the hole flows from the source to the drain. In the p-type transistor, because the hole flows from the source to the drain, a current may flow from the source to the drain. On the other hand, in the n-type transistor, because a carrier is an electron, a source voltage may be lower than a drain voltage so that the electron flows from the source to the drain. In the n-type transistor, because the electron flows from the drain to the source, a current may flow from the drain to the source. However, a source and a drain of a transistor may switch therebetween based on a voltage applied thereto. Based thereon, in the following description, one of a source and a drain will be described as a first electrode, and the other of the source and the drain will be described as a second electrode.
As illustrated in
A video supply unit 110 (a set or a host system) may output a video data signal supplied from the outside or various driving signals and an image data signal (a video data signal) stored in an internal memory thereof. The video supply unit 110 may supply a data signal and the various driving signals to the timing controller 120.
The timing controller 120 may output a gate timing control signal GDC for controlling an operation timing of the gate driver 130, a data timing control signal DDC for controlling an operation timing of the data driver 140, and various synchronization signals. The timing controller 120 may provide the data driver 140 with the data timing control signal DDC and a data signal DATA supplied from the video supply unit 110. The timing controller 120 may be implemented as an integrated circuit (IC) type and may be mounted on a printed circuit board (PCB), but is not limited thereto.
The gate driver 130 may output a gate signal (or a gate voltage) in response to the gate timing control signal GDC supplied from the timing controller 120. The gate driver 130 may supply the gate signal to a plurality of subpixels, included in the display panel 150, through a plurality of gate lines GL1 to GLm. The gate driver 130 may be implemented as an IC type or may be directly provided on the display panel 150 in a gate in panel (GIP) type, but is not limited thereto.
In response to the data timing control signal DDC supplied from the timing controller 120, the data driver 140 may sample and latch the data signal DATA, convert a digital data signal into an analog data voltage, based on a gamma reference voltage, and output the analog data voltage. The data driver 140 may respectively supply data voltages to the subpixels of the display panel 150 through a plurality of data lines DL1 to DLn. The data driver 140 may be implemented as an IC type or may be mounted on the display panel 150 or a PCB, but is not limited thereto.
The power supply 180 may generate a high-level voltage and a low-level voltage, based on an external input voltage supplied from the outside, and may output the high-level voltage and the low-level voltage through a high-level power line EVDD and a low-level power line EVSS. The power supply 180 may generate and output a voltage (a gate high voltage and a gate low voltage) needed for driving of the gate driver 130 or a voltage needed for driving of the data driver 140, in addition to the high-level voltage and the low-level voltage.
The display panel 150 may display an image (video), based on a driving voltage including the high-level voltage and the low-level voltage and a driving signal including the gate signal and a data voltage. The subpixels of the display panel 150 may each self-emit light. The display panel 150 may be manufactured based on a substrate, having stiffness or flexibility, such as glass, silicon, or polyimide. Also, the subpixels emitting light may include pixels including red, green, and blue, or may include pixels including red, green, blue, and white.
For example, one subpixel SP may be connected to a first data line DL1, a first gate line GL1, the high-level power line EVDD, and the low-level power line EVSS and may include a pixel circuit which includes a switching transistor, a driving transistor, a capacitor, and an organic light emitting diode. The subpixel SP used in the light emitting display apparatus may self-emit light and may be complicated in configuration of a circuit. Also, an organic light emitting diode emitting light may be diversified, and a compensation circuit which compensates for a degradation in a driving transistor supplying a driving current needed for driving of the organic light emitting diode may be diversified. Accordingly, the subpixel SP may be simply illustrated in a block shape.
Hereinabove, each of the timing controller 120, the gate driver 130, and the data driver 140 has been described as an individual element. However, based on an implementation type of the light emitting display apparatus, one or more of the timing controller 120, the gate driver 130, and the data driver 140 may be integrated into one IC.
As illustrated in
The clock signal CLKS may be output through clock signal lines, and the start signal VST may be output through a start signal line. The shift register 131 may operate based on the clock signals CLKS and the start signal VST and may output gate signals Gout[1] to Gout[m].
As illustrated in
As illustrated in
An example where the first and second shift registers 131a and 131b are respectively disposed in the left and right non-display areas NA of the display panel 150, but embodiments of the present disclosure are not limited thereto.
As illustrated in
The pseudo generator 133 (e.g., a circuit) may be disposed in a non-display area NA located at an upper side of a display area AA, and the pseudo pattern parts 134a and 134b may be respectively disposed in non-display areas NA located at left and right sides of the display area AA. The pseudo pattern parts 134a and 134b (e.g., circuits) may include first and second pseudo pattern parts 134a and 134b which are disposed to correspond to the first and second shift registers 131a and 131b, respectively. The first and second pseudo pattern parts 134a and 134b may be implemented with a conductive pattern configuring a specific shape so as to offset and minimize an electric field causing electromagnetic interference (EMI).
In
As illustrated in
The pseudo generator 133 may include a current sensing circuit 133a, a phase inverting circuit 133b, and a current summation circuit 133c.
The current sensing circuit 133a may sense the clock signals output from the level shifter 135 and applied to the first and second shift registers 131a and 131b to output as a current type. The current sensing circuit 133a may include an input terminal connected to a clock signal output terminal of the level shifter 135 and an output terminal connected to a clock signal input terminal of each of the first and second shift registers 131a and 131b. That is, clock signal lines CLKL transferring the clock signals may be disposed between the level shifter 135 and the first and second shift registers 131a and 131b and may be interconnected to pass through the current sensing circuit 133a.
The phase inverting circuit 133b may invert (180-degree invert) phases of the clock signals which are sensed by the current sensing circuit 133a and are output as a current type, and thus, may output clock signals as an inverted current type.
The current summation circuit 133c may summate and output one or more of inverted currents of clock signals which are output through inversion by the phase inverting circuit 133b. A summation current output from the current summation circuit 133c may be applied to the first and second pseudo pattern parts 134a and 134b.
As illustrated in
Hereinafter, based on a second embodiment, a portion associated with the pseudo generator 133 may be specified, and an effect based thereon will be described.
As illustrated in
The control board CPCB may include a timing controller 120 and a level shifter 135. The timing controller 120 may output clock signals CLKS including first clock signals G1, second clock signals G2, and third clock signals EM. For example, the first clock signals G1 may be used as clock signals for generating a first scan signal in a gate signal, the second clock signals G2 may be used as clock signals for generating a second scan signal in the gate signal, and the third clock signals EM may be used as clock signals for generating an emission signal in the gate signal.
The level shifter 135 may up-shift and output levels of the clock signals CLKS. The level shifter 135 may up-shift levels of the clock signals CLKS, based on a gate high voltage and a gate low voltage output from a power supply, but embodiments of the present disclosure are not limited thereto.
Hereinafter, in the second embodiment, an example where four-phase first clock signals G1, five-phase second clock signals G2, and two-phase third clock signals EM are output from the timing controller 120 will be described.
The control board CPCB and the source board SPCB may be electrically connected to each other by the first connector CNT1. The source board SPCB and the display panel 150 may be electrically connected to each other by the second connector CNT2.
Clock signal lines CLKL transferring the clock signals CLKS may be disposed in the first connector CNT1, the source board SPCB, the second connector CNT2, and the display panel 150. An example may be described where the clock signal lines CLKL are divisionally disposed on the source board SPCB so as to smoothly transfer the clock signals to first and second shift registers 131a and 131b respectively disposed in left and right non-display areas NA of the display panel 150.
The display panel 150 may include the first and second shift registers 131a and 131b, the pseudo generator 133, and the first and second pseudo pattern parts 134a and 134b. The pseudo generator 133 may solve a problem of radiation mismatching between pseudo signals generated from the pseudo pattern parts 134a and 134b and clock signals which are output from the level shifter 135 and are applied to the first and second shift registers 131a and 131b.
The pseudo generator 133 may include a current sensing circuit 133a, a phase inverting circuit 133b, and a current summation circuit 133c. A function of each of the current sensing circuit 133a, the phase inverting circuit 133b, and the current summation circuit 133c may refer to the first embodiment.
As illustrated in
The current sensing and phase inverting circuit 133a & 133b may be implemented as a current mirror type. The current sensing and phase inverting circuit 133a & 133b may include a first transistor FET1 and a second transistor FET2.
The first transistor FET1 may include a first electrode (a source electrode) connected to an input terminal, a second electrode (a drain electrode) connected to an output terminal, and a gate electrode connected to the output terminal and a gate electrode of the second transistor FET2. The second transistor FET2 may include a first electrode (a source electrode) connected to the first or second pseudo pattern part 134a or 134b, a second electrode (a drain electrode) connected to a ground terminal, and a gate electrode connected to the output terminal and the gate electrode of the first transistor FET1.
Hereinafter, an operation of outputting, as a phase-inverted current type, a first clock signal applied to the current sensing and phase inverting circuit 133a & 133b will be described.
A first clock signal CLK input as a voltage type may be generated as a first reference current Iref and may be output through the first or second shift register 131a or 131b, based on an operation of the first transistor FET1.
The second transistor FET2 may operate identical to the first transistor FET1 and may perform a sensing operation (a current mirror operation) of generating the same first mirror current Imr as the first reference current Iref through the second electrode and outputting it to the ground terminal. Also, the second transistor FET2 may perform a phase inverting operation of generating a first inverted current Ips opposite to the first reference current Iref through the first electrode and outputting it to the first or second pseudo pattern part 134a or 134b. On the contrary to the first transistor FET1, because the first electrode (the source electrode) of the second transistor FET2 is connected to the first or second pseudo pattern part 134a or 134b, a current may flow in a reverse direction opposite to a sensed current, and thus, the second transistor FET2 may generate a phase-inverted current.
As described above, the current sensing and phase inverting circuit 133a & 133b may sense a current flowing in a clock signal through a current mirror and may allow a current to flow in a reverse direction opposite to a sensed current, and thus, may invert a phase of an input current to output a phase-inverted current.
Hereinafter, an operation of generating a pseudo signal corresponding to a clock signal(s) output from the level shifter 135 illustrated in
As illustrated in
First reference currents Iref1 to Iref4, first mirror currents Imr1 to Imr4, and first inverted currents Ips1 to Ips4 may be generated from the first clock signals G1_CLK1 to G1_CLK4 by the current sensing and phase inverting circuit 133a & 133b. Also, the first inverted currents Ips1 to Ips4 may be applied to the first or second pseudo pattern part 134a or 134b and may then be summated (Ipsum′), and thus, one pseudo signal may be generated.
As illustrated in
1st′ reference currents Iref1′ to Iref5′, 1st′ mirror currents Imr1′ to Imr5′, and 1st′ inverted currents Ips1′ to Ips5′ may be generated from the second clock signals G2_CLK1 to G2_CLK5 by the current sensing and phase inverting circuit 133a & 133b. Also, the 1st′ inverted currents Ips1′ to Ips5′ may be applied to the first or second pseudo pattern part 134a or 134b and may then be summated (Ipsum'), and thus, one pseudo signal (Pseudo) may be generated.
As illustrated in
1st″ reference currents Iref1″ and Iref2″, 1st″ mirror currents Imr1″ and Imr2″, and 1st″ inverted currents Ips1″ and Ips2″ may be generated from the third clock signals EM_CLK1 and EM_CLK2 by the current sensing and phase inverting circuit 133a & 133b. Also, the 1st″ inverted currents Ips1″ and Ips2″ may be applied to the first or second pseudo pattern part 134a or 134b and may then be summated (Ipsum′), and thus, one pseudo signal (Pseudo) may be generated.
In
Furthermore, a pseudo signal may be used for offsetting and minimizing an electric field causing EMI of a pulse-type signal which is repeated with specific periodicity like the first clock signals G1_CLK1 to G1_CLK4, the second clock signals G2_CLK1 to G2_CLK5, and the third clock signals EM_CLK1 and EM_CLK2. A pseudo signal of a voltage type may be used, but a problem of radiation mismatching may occur due to various causes such as a line load, a driving environment, and a peripheral circuit.
For example, the first and second shift registers 131a and 131b may be large in load because of being connected to subpixels included in a display area, but the first and second pseudo pattern parts 134a and 134b may be small in load because of being connected to a pattern included in a non-display area (occupying a relatively small area). Therefore, in a case which generates a pseudo signal of a voltage type, a problem of radiation mismatching (caused by a reduction in electric field offset efficiency based on the use of a pseudo signal) may occur due to consumption current mismatching caused by a load difference between the first and second shift registers 131a and 131b and the first and second pseudo pattern parts 134a and 134b.
However, a pseudo signal of a current type may be robust to a cause which causes a variation of a signal, compared to the pseudo signal of a voltage type. Accordingly, when a pseudo signal of a current type is generated based on the pseudo generator 133 according to the first embodiment and is applied to the first and second pseudo pattern parts 134a and 134b, robustness to a load difference and noise may increase, and an electric field causing EMI may be offset and minimized.
Furthermore, when a pseudo signal corresponding to clock signals is generated as a current type and at least one of the pseudo signals are summated as one, an integration design of the pseudo pattern parts 134a and 134b may be performed, and an area occupied by the pseudo pattern parts 134a and 134b may be reduced, thereby reducing a bezel region of a display panel.
As seen through comparison between the graphs of
This may be because, as seen in
Moreover, in the present disclosure, an example which generates pseudo signals on only clock signals is illustrated and has been described. However, the pseudo generator may be applied to a pulse-type signal which is repeated with specific periodicity, like a multiplexer signal needed for driving of a display panel as well as the clock signals.
Hereinabove, may solve a problem of radiation mismatching caused by a load difference between a shift register and a pseudo pattern part, may increase robustness to noise, and may offset and minimize an electric field causing EMI. Also, the present disclosure may generate a pseudo signal of a current type corresponding to clock signals and may summate at least one of the pseudo signals to not only achieve an integration design of the pseudo pattern part, but also decrease an area occupied by a pseudo pattern part, thereby reducing a bezel region of a display panel.
The effects according to the present disclosure are not limited to the above examples, and other various effects may be included in the specification.
While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0197122 | Dec 2023 | KR | national |
