Claims
- 1. A pseudorandom number generator comprising:
- a polynomial circuit comprising a feedback shift register; and
- matrix multiplication means for receiving parallel data from said feedback shift register and performing matrix multiplication A.times.G wherein A is a vector and G is a matrix.
- 2. A pseudorandom number generator comprising:
- a polynomial circuit shift register storing a vector A;
- an exclusive-OR gate receiving as inputs two bit values of said shift register, the output of said exclusive-OR gate being input to said shift register; and
- means for matrix multiplying the vector A in said shift register by a shuffling matrix G wherein the multiplying of one A vector after another by the matrix G produces asymptotic random numbers in succession.
- 3. A pseudorandom number generator comprising:
- an M-sequence generator having a plurality of stages a.sub.i ; and
- a matrix product circuit which combines a matrix G having components g.sub.ji with the stages a.sub.i to provide output elements b.sub.j of a number, each b.sub.j being represented by the expression,
- b.sub.j =.sub.i.sup..SIGMA. a.sub.i g.sub.ji
- wherein the numbers formed of b.sub.j elements are asymptotic random numbers having a uniform k distribution.
- 4. A pseudorandom number generator as in claim 3 wherein each row vector of G is linear and independent.
- 5. A pseudorandom number generator as in claim 3 wherein the M-sequence generator comprises (a) shift register and (b) a gate which exclusively ORs at least two stages of the shift register and directs the result as input to a stage of the shift register.
- 6. A pseudorandom number generator as in claim 5 wherein the shift register has seven stages and wherein said gate exclusively ORs the bit of one end stage a.sub.0 with the bit of the middle stage a.sub.3, the result being input to bit of the other end stage a.sub.6.
- 7. A method for generating l-bit pseudorandom numbers by using a feedback shift register having a polynomial characteristic equation of degree p, said shift register having stages which contain bit values where l is less than or equal to p, the method comprising the steps of:
- combining the current bit values of preselected stages of the shift register, the combined result being shifted into the shift register as the next input;
- forming a matrix G; and
- multiplying, in a matrix product circuit, the bit values contained in the stages of the shift register by the formed matrix G for successive shift register shifts, wherein successive products of the multiplying in response to successive shifts represents successive uniform k-distribution random numbers characterized by asymptoticity.
- 8. The method of claim 7 wherein the step of forming the matrix G comprises the step of:
- forming one G.sub.L matrix after another for successive values of L, where L is less than or equal to p, wherein each matrix G.sub.L has rows which are linear and independent;
- the G.sub.L matrix, for the highest L, comprising the G matrix.
- 9. The method of claim 8 wherein the forming of G.sub.L matrixes comprises the steps of:
- for L=1, selecting an arbitrary row vector v.sub.L and deriving the remaining row vectors from v.sub.L ;
- for L greater than 1, (i) extracting some row vectors from previously formed matrixes of lesser L value and (ii) arbitrarily selecting a vector v.sub.L for a non-extracted row and deriving the remaining non-extracted rows from the selected vector v.sub.L ; and
- for each L, re-selecting the vector v.sub.L if each row vector in matrix G.sub.L is not linear and independent and re-deriving the remaining rows for the matrix G.sub.L with the re-selected vector v.sub.L ;
- row vectors in each G.sub.L matrix being extracted from only a previously formed G.sub.L matrix having only linear and independent rows.
Priority Claims (1)
| Number |
Date |
Country |
Kind |
| 59-214467 |
Oct 1984 |
JPX |
|
Parent Case Info
This is a continuation of application Ser. No. 06/773,486, filed on Sept. 9, 1985, now abandoned.
US Referenced Citations (6)
Foreign Referenced Citations (2)
| Number |
Date |
Country |
| 2172460 |
Sep 1973 |
FRX |
| 2163627 |
Feb 1986 |
GBX |
Non-Patent Literature Citations (1)
| Entry |
| Latawiec, K. J., "New Method of Generation of Shifted Linear Pseudorandom Binary Sequences," Proc. IEEE, vol. 121, No. 8, Aug. 1974, pp. 905-906. |
Continuations (1)
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Number |
Date |
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| Parent |
773486 |
Sep 1985 |
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