Pull-up circuit for an input buffer

Abstract

An input buffer has a high voltage leg in parallel with a low voltage leg. The low voltage leg pulls up the pad when the pad voltage is below the power supply voltage. The high voltage leg remains off when the pad voltage is below the power supply. The low voltage leg is turned off when the pad voltage is above the power supply voltage. The high voltage leg is on when the pad voltage is above power supply voltage. A low voltage bias circuit and a high voltage bias circuit protect the transistors in the low and voltage legs when the pad voltage is above the power supply voltage. As a result, the pull-up circuit is high voltage tolerant and does not sink the current from pad.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a prior art pull-up circuit for an input buffer;

FIG. 2 is a circuit diagram of a pull-up circuit for an input buffer in accordance with one embodiment of the invention;

FIG. 2A is a graph of the voltage at the node nsub of the pull-up circuit of FIG. 2 versus the pad voltage in accordance with one embodiment of the invention;

FIG. 2B is a graph of the voltage at the node pull of the pull-up circuit of FIG. 2 versus the pad voltage in accordance with one embodiment of the invention;

FIG. 2C is a graph of the pad current of the pull-up circuit of FIG. 2 versus the pad voltage in accordance with one embodiment of the invention;

FIG. 3 is a circuit diagram of a pull-up circuit for an input buffer in accordance with one embodiment of the invention;

FIG. 3A is a circuit diagram of a high voltage leg bias circuit in accordance with one embodiment of the invention;

FIG. 3B is a graph of the voltage at the node nsub of the pull-up circuit of FIG. 3 versus the pad voltage in accordance with one embodiment of the invention;

FIG. 3C is a graph of the voltage at the node pull of the pull-up circuit of FIG. 3 versus the pad voltage in accordance with one embodiment of the invention; and

FIG. 3D is a graph of the pad current of the pull-up circuit of FIG. 3 versus the pad voltage in accordance with one embodiment of the invention.

Claims

1. A pull-up circuit for an input buffer, comprising: a pad;a first pmos transistor having a source and a drain;a second pmos transistor having a source and a drain, wherein the first and second pmos transistors are coupled in series, and the drain of the second pmos transistor is coupled to the pad;a first node coupled to substrates of the first pmos transistor and the second pmos transistor; anda power supply coupled to the source of the first pmos transistor.

2. The circuit of claim 1, further comprising a resistor coupled to a drain of a third pmos transistor and coupled to the pad, where a source of the third pmos transistor is coupled to power and a gate of the third pmos transistor is coupled to the output of a pmos-nmos stack.

3. The circuit of claim 2, further comprising where the gates of the pmos-nmos stack are coupled together, and a source of the pmos in the pmos-nmos stack is coupled to the pad, and the drain of the nmos in the pmos-nmos stack is coupled to ground

4. The circuit of claim 1, wherein the first node is coupled to the drain of the first pmos transistor.

5. The circuit of claim 4, wherein a gate of the first pmos transistor is coupled to the pad.

6. The circuit of claim 5, wherein a gate of the second pmos transistor is coupled to the power supply voltage.

7. A pull-up circuit for an input buffer, comprising: a pmos transistor having a draina pad electrically coupled to the drain of the pmos transistor; anda resistor electrically coupled to the drain of the pmos transistor.

8. The circuit of claim 7, further including a second pmos transistor having a drain coupled to a source of the pmos transistor.

9. The circuit of claim 8, wherein a gate of the second pmos transistor is coupled to the pad.

10. The circuit of claim 8, wherein a gate of the first pmos transistor is coupled to a power supply voltage.

11. The circuit of claim 8, wherein the source of the pmos transistor is coupled to an n-well of the pmos transistor and coupled to an n-well of the second pmos transistor.

12. The circuit of claim 7, further including a third pmos transistor having a drain coupled to the resistor.

13. The circuit of claim 12, wherein a gate of the third pmos transistor is coupled to a low voltage gate bias circuit.

14. The circuit of claim 13, wherein the low voltage gate bias circuit has a pmos transistor with a source coupled to the pad and a source coupled to a source of an nmos transistor, a gate of the pmos transistor and a gate of the nmos transistor is coupled to the power supply voltage.

15. A pull-up circuit for an input buffer, comprising: a pad;a high voltage pull-up leg having a node coupled to the pad;a low voltage pull-up leg electrically in parallel with the high voltage pull-up leg.

16. The circuit of claim 15, further including a low voltage gate bias circuit coupled to the low voltage pull-up leg.

17. The circuit of claim 16, further including a high voltage gate bias circuit coupled to the high voltage pull-up leg.

18. The circuit of claim 15, wherein the high voltage pull-up leg includes a first pmos transistor having a drain coupled to the pad and a second pmos transistor having a drain coupled to a source of the first pmos transistor.

19. The circuit of claim 18, wherein an n-well of the first pmos transistor is electrically coupled to an n-well of the second pmos transistor.

20. The circuit of claim 19, wherein a gate of the second pmos transistor is electrically coupled to the pad.