Pulse compressor for multiplexed noise codes

Abstract

A pulse compressor for multiplexed noise codes generated with transposed code mate pairs and which comprise expanded noise codes of the code mates where the first expanded code is generated by delaying the inverse of one code mate by a predetermined time delay and adding it to the other code mate and wherein the second expanded code is generated by delaying the inverse of the other code mate, forming its complement and adding it to said one code mate. The means utilized comprises means for compressing the two expanded codes collectively by summing and differencing of the codes in a repetitive pipelined sequence until a final pair of codes are outputted which are lobeless and equal to the basic mate pair.

Description

CROSS REFERENCE TO RELATED APPLICATION

This invention is related to the co-pending application Ser. No. 449,029 entitled, "Multiplexed Noise Code Generator Utilizing Transposed Codes" (CERCOM D-2037) filed in the name of Frank S. Gutleber, the present inventor, on Dec. 13, 1982.

1. Field of the Invention

This invention relates generally to multiplexed noise codes having autocorrelation functions which upon matched filter detection provide an impulse, i.e., a lobeless autocorrelation function and more particularly to the compression of expanded multiplexed noise codes into a basic code mate pair which are lobeless.

2. Background of the Invention

Noise codes comprised of what is termed code mate pairs are well known. Such codes have autocorrelation functions which upon matched filter detection provide lobeless impulse signals. It is also well known that typical means of compressing such a code mate pair is to employ a passive matched filter in the form of a separate tapped delay line for each code, with the output of the taps matched to the input code bits in reverse order to the input sequence. The linear summation of the matched outputs of each delay line then provides the compressed code for each code of the mate pair. Each output is equal to the autocorrelation function of the respective code being detected and the simple linear sum of the two outputs results in a lobeless compressed mate pair.

Such a configuration becomes relatively expensive and difficult to implement for very long codes since a separate tap with or without an inverter is required for each bit of the input code. Such long codes typically comprise expanded codes from a basic code mate pair and typically involves butting, interleaving, partial interleaving, or overlapping one code mate with the other code mate where, for example, one of the codes is delayed by a value equal to the code length of the two mate pairs in the expansion process. A typical example of such techniques is shown and described in U.S. Pat. No. 3,461,451, entitled, "Code Generator To Produce Permutations Of Code Mates," issued to Frank S. Gutleber, the present inventor, on Aug. 12, 1969. Another example comprises codes generated in accordance with the invention disclosed in the above referenced co-pending application entitled, "Multiplexed Noise Code Generator Utilizing Transposed Codes," wherein expanded multiplexed noise codes including code mate pairs having autocorrelation functions, which upon detection provide an impulse autocorrelation function, are generated by delaying the inverse of one of the code mate pairs by a value equal to the code length and adding it to the other code mate pair to form a first expanded code mate, while a second expanded code mate is generated by delaying the inverse of the other code also by a value equal to the code length, forming the complement thereof and adding it to the first mentioned code mate, forming what is generally referred to as transposed codes. It is to this latter type of code generation that the present invention particularly pertains.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide an improvement in the detection of multiplexed noise codes.

Another object of the invention is to provide improvement in the compression of multiplexed noise codes.

Still another object of the present invention is to provide an improvement in the compression of expanded multiplexed noise code pairs.

And yet another object of the present invention is to provide an improvement in the compression of expanded multiplexed noise codes generated with transposed codes of multiplexed noise code mate pairs.

These and other objects are achieved by a means for compressing a pair of expanded codes which have been generated from a basic code mate pair where the first expanded code is comprised of the combination of one code mate and the inverse of the other while the other expanded code is comprised of the combination of the other basic code mate and the inverse complement of the first code mate. Code compression of the expanded code mate pairs is accomplished collectively rather than individually by a repetitive summing and subtracting process in successive stages whereby the coherent compression of the expanded code back down to a lobeless basic mate pair is accomplished. In one embodiment, one expanded mate pair is summed with the inverse of the other expanded mate pair, thereby forming a first compressed code mate of one half the original code length, while a second compressed code mate of half the code length is formed by differencing the second expanded code mate and the inverse of the first expanded code mate. In a second embodiment, the compression is obtained with only a single code sequence inversion and appropriate time delays.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram illustrative of a first embodiment for compressing expanded multiplexed noise code pair mates in accordance with the subject invention; and

FIG. 2 is a functional block diagram illustrative of a second embodiment for compressing expanded multiplexed noise code pair mates in accordance with the subject invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention is directed to compression of a type of expanded multi-bit digital codes referred to as noise codes, meaning that they have autocorrelation functions which upon detection provides an impulse. In particular, one class of noise codes are known wherein pairs of coded signals termed "code mates" have respective autocorrelation functions which provide a peak output at a given time and a zero output or outputs having the same magnitude but opposite polarity at all other times. When code mates, for example, are orthogonally multiplexed, matched filter detected and linearly added, there is provided a lobeless impulse output of a relatively high amplitude at a given time and a zero output at all other times.

Expressed mathematically, for a pair of code mates a and b, .phi..sub.a (.tau.)=-.phi..sub.b (.tau.) for all .tau..noteq.0, where .phi..sub.a (.tau.) is the autocorrelation function of code a and .phi..sub.b (.tau.) is the autocorrelation function of code b.

The pulse compression to be subsequently described provides an improved means for compressing to a lobeless impulse a multiplexed noise code pair for code mates that are expanded in accordance with the following expression:

Code A=a, b (1) Code B=b, a (2) Where A and B comprise an expanded code mate pair generated from Codes a and b which comprise a basic mate pair, and wherein: x is the inverse of code sequence x, i.e. x.sub.1, x.sub.2, x.sub.3 becomes x.sub.3, x.sub.2, x.sub.1 ; x0 is the negative or complement of code x; and the (,) in a code sequence x, y signifies that the subelement or code sequence y follows code sequence x by some time delay .tau..sub.i.

In the expansion process of code mate pairs in accordance with equations (1) and (2), any one of the four subelements or code sequences (a, b, a or b) making up the expanded code can be inverted or complemented as well as interchanged such that for example,

Code A=a, b (3) Code B=b, a (4) or, Code A=b, a (5) Code B=a, b (6) In all such instances, the expanded code pairs A and B meet the requirements for forming a code mate pair.

In view of the foregoing, consider now the following code mate pair A=a.sub.3 and B=b.sub.3 that is generated in accordance with repeated application of the expansion rules set forth in equations (1) and (2), bearing in mind that expansions according to equations (3) through (6) could also be utilized, when desired. For a basic code mate pair a and b, a first expansion results in codes a.sub.1, b.sub.1 being developed as follows:

a.sub.1 =a, b (7) b.sub.1 =b, a (8) Expanding code mates a.sub.1 and b.sub.1 in a second expansion process provides a mate pair a.sub.2 and b.sub.2, which can be expressed as follows: a.sub.2 =a.sub.1, b.sub.1 =a, b, a, b (9) b.sub.2 =b.sub.1, a.sub.1 =b, a, b, a (10) A third expansion, involving now the code mates a.sub.2 and b.sub.2, results in code mates a.sub.3 and b.sub.3 being developed in the following manner: a.sub.3 =a.sub.2, b.sub.2 =a, b, a, b, a, b, a, b (11) b.sub.3 =b.sub.2, a.sub.2 =b, a, b, a, b, a, b, a (12)

As is known, having been shown and described, for example, in the above reference related application Ser. No. 449,029, entitled, "Multiplexed Noise Code Generator Utilizing Transposed Codes," codes a.sub.3 and b.sub.3 form a mate pair wherein .phi.a.sub.3 (.tau.)=-.phi.b.sub.3 (.tau.) for all .tau..noteq.0 and accordingly can be compressed to a lobeless impulse. The present invention accordingly is directed to a means for compressing expanded code mate pairs such as developed in equations (7) through (12) in a collective manner rather than individually, as in prior art practice, where separate tapped delay lines for each code are used and wherein the output of the taps of the delay lines are matched to the input code bits in reverse order to the input sequence providing thereby a complex conjugate of the input bits.

The present invention results from an inspection of the foregoing expansion process which reveals that a repeated application of the following general operation will coherently compress the expanded code mate back to a lobeless basic mate pair, namely:

a.sub.i-1 =a.sub.i +b.sub.i (13) b.sub.i-1 =b.sub.i -a.sub.i (14) An appropriate time delay .tau..sub.i is required to line up the compressed bits at each stage and/or account for the delay introduced with the code inverter where, for example, the inverter comprises a last-in/first-out (LIFO) code sequence inverter.

Since equations (13) and (14) involve code inversions of the expanded codes A=a.sub.3 and code B=b.sub.3 as expressed in equations (11) and (12), inverted sequences thereof, i.e. a.sub.3 and b.sub.3 can be expressed as follows:

A=a.sub.3 =b, a, b, a, b, a, b, a (15) B=b.sub.3 =a, b, a, b, a, b, a, b (16)

Applying code compression equation (13) to codes a.sub.3 and b.sub.3 results in a code sequence a.sub.2 being obtained which is one half the code length of a.sub.3 and which is formed as illustrated below as: ##EQU1## where the exponent indicates the amplitude of the respective codes.

In a like manner, the code mate b.sub.2 is developed in accordance with equation (14) in the following manner: ##EQU2##

The inversion process in developing equation (17) means inverting not only the code sequence of b.sub.3 but also changing all the subelements so that, for example, x becomes x and x becomes x. In the difference equation (18) the subtracted term, i.e. a.sub.3 is complemented such that x becomes x0 and x0 becomes x and a summation is thereafter made.

Similarly, compressed code mates a.sub.1 and b.sub.1 are obtained in accordance with the foregoing mathematical operations as follows: ##EQU3## and, ##EQU4##

A third compression results in providing the basic code mates a and b but whose amplitude is amplified by a factor of 8. This is obtained as shown below: ##EQU5## and, ##EQU6##

Referring now to FIG. 1, there is disclosed a functional block diagram of means which is operable to compress the expanded code mate pair a.sub.3 and b.sub.3 in conformance with equations (13) and (14). As shown, the code compressor is comprised of a combination of linear adders, last-in/first-out (LIFO) shift registers which operate as sequence inverters to invert a sequence where, for example, x.sub.1, x.sub.2, x.sub.3 becomes x.sub.3, x.sub.2, x.sub.1 and signal inverters which operate to provide the complement of the input code, for example, x becomes x

The compressor shown in FIG. 1 is comprised of three compressor stages 10.sub.1, 10.sub.2 and 10.sub.3. The first stage 10.sub.1 is shown coupled to a pair of input codes comprising the code mate pair a.sub.3 and b.sub.3 which is compressed in stage 10.sub.1 to half their respective lengths by means of a linear adder 12.sub.1 and a LIFO shift register 14.sub.1 directly coupled to the expanded code mate a.sub.3 while the other code mate b.sub.3 is directly coupled to a second linear adder 16.sub.1 and a second LIFO shift register 18.sub.1. A signal inverter 20.sub.1 is coupled between the LIFO shift register 14.sub.1 and a second linear adder 16.sub.1. A clock 22 is coupled to the two LIFO shift registers 14.sub.1 and 18.sub.1 in order to control the read in and read out times of the code sequences of a.sub.3 and b.sub.3, respectively. It can be seen that the linear adder 12.sub.1 is operable to add the inverted sequence of code b.sub.3 to the sequence of a.sub.3 and thus implement equation (13) and output a compressed code mate a.sub.2. Code a.sub.3 has its bit sequence inverted in the LIFO shift register 14.sub.1, is complemented with the signal inverter 20.sub.1 and added to code b.sub.3 in the linear adder 16.sub.1 to implement equation (14) and output a compressed code mate b.sub.2.

In a similar manner, the once compressed code mates a.sub.2 and b.sub.2 are fed to the second compressor stage 10.sub.2 where a compressed code mate a.sub.1 equal to one half the code length of a.sub.2 is obtained by inverting the code b.sub.2 and adding it to the code a.sub.2. In a similar manner, the code sequence of a.sub.2 is inverted, complemented and added to the code b.sub.2 to compress to the code mate b.sub.1. Duplicating this process once more in the third compressor stage 10.sub.3 then compresses the code mate pairs a.sub.1 and b.sub.1 down to the output codes which comprise the basic code mate pairs a and b and which are not only lobeless, but are obtained with significantly less hardware than what is required for conventional compressors.

It should be pointed out that only p compression stages are required to compress an n bit code length down to a single impulse where 2.sup.p =n. For example, only 10 compression stages would be required to compress a 1024 bit noise code structure down to a lobeless impulse.

An alternative approach to the expanded code compression process will now be described. Assuming for example that the previously disclosed code mate pairs a.sub.3 and b.sub.3 require compression to a lobeless impulse, if the expanded code b.sub.3 is first inverted to b.sub.3, then a simple sum and difference with appropriate delays at each subsequent stage will compress the mate pair a.sub.3 and b.sub.3 down to the basic code mates a and b in the following manner.

At the first stage the codes a.sub.3 and b.sub.3 are added as shown below to provide the code a.sub.2 as follows: ##EQU7##

Likewise, the code a.sub.3 is subtracted from b.sub.3 to provide the code b.sub.2, as: ##EQU8## In the next or second compression stage, the code a.sub.2 is delayed by a time delay .tau..sub.2 to yield a code a'.sub.2 which is illustrated below as:

a'.sub.2 =a.sub.2 (t+.tau..sub.2)=., ., ., ., a.sup.2,b.sup.2,a.sup.2,b.sup.2 (25)

The codes a'.sub.2 and b.sub.2 are then summed in the following manner to provide the code a.sub.1 : ##EQU9##

As before, the difference between codes b.sub.2 and a'.sub.2 yield the compressed code b.sub.1 which is illustrated below as: ##EQU10##

In the third compression stage, the compressed code a.sub.1 is delayed by a time delay .tau..sub.1 to provide the code a'.sub.1 which is illustrated below as:

a'.sub.1 =a.sub.1 (t+.tau..sub.1)=., ., ., ., ., ., a.sup.4, b.sup.4 (28)

As before, the compressed codes a'.sub.1 and b.sub.1 are summed together to provide the basic code mate a which has an amplitude increased by a factor of 8 which is illustrated below as: ##EQU11##

Similarly, the codes b.sub.1 and a'.sub.1 are differenced to provide the basic code mate b which also has an amplitude increased by a factor of 8 and which is also illustrated as: ##EQU12##

Referring now to FIG. 2, there is disclosed a functional block diagram of a circuit configuration which is operable to compress the expanded code mate pair a.sub.3 and b.sub.3 in accordance with the above disclosed alternate approach. As shown in FIG. 2, the code compressor is comprised of three compressor stages 24.sub.1, 24.sub.2 and 24.sub.3. The first compressor stage 24.sub.1 is adapted to receive as inputs the expanded codes a.sub.3 and b.sub.3 which compress to half their code lengths by means of a pair of linear adders 26.sub.1 and 28.sub.1 as well as a LIFO shift register 30.sub.1 and a signal inverter 32.sub.1. The LIFO shift register 30.sub.1 is coupled to and inverts the code b.sub.3 which is applied to the linear adder 26.sub.1 along with the code a.sub.3 whereupon a compressed code a.sub.2 is provided in accordance with equation (23). The input code a.sub.3 is also applied to the inverter 32.sub.1 where the complement thereof is applied to the second linear adder 28.sub.1 along with the inverted code b.sub.3 to provide the compressed code output b.sub.2 in accordance with equation (24).

The second compressor stage 24.sub.2 includes a first time delay means 34.sub.2 in the signal channel coupled to the linear adder 26.sub.2. The LIFO shift register 30.sub.1 which is included in the first stage 24.sub.1, is not required and the compressed code b.sub.2 is applied directly to the linear adders 26.sub.2 and 28.sub.2. The time delay circuit 34.sub.2 provides a time delay .tau..sub.2 which is equal to the code length of code b.sub.2. The output of the delay circuit 34.sub.2 is applied as the code a'.sub.2 to the inverter 32.sub.2 and the linear adder 26.sub.2. The linear adder 26.sub.2 accordingly operates to combine the codes a'.sub.2 and b.sub.2 to provide the compressed code a.sub.1 in accordance with equation (26). The linear adder 28.sub.2 adds the complement of the code a'.sub.2 to the code b.sub.2 to provide an output of the compressed code b.sub.1 in accordance with equation (27).

The third compressor stage 24.sub.3 is identical in configuration to the second compressor stage 24.sub.2 with the exception that the time delay means 34.sub.3 provides a time delay of .tau..sub.1 =0.5 .tau..sub.2 and provides an output code a'.sub.1 in accordance with equation (28). The linear adder 26.sub.3 adds the codes a'.sub.1 and b.sub.1 to output the basic code mate a according to equation (29). Similarly, the second linear adder 28.sub.3 sums the complement of the code a'.sub.1 with the code b.sub.1 to output the other basic code mate b in accordance with equation (30).

The embodiment of the invention shown in FIG. 2 has somewhat of a practical advantage over the embodiment shown in FIG. 1, notwithstanding the requirement of a time delay in each compression stage. This advantage results from the elimination of all but one code sequence inverter which, if optimum coherent compression is to be realized, cannot be a relatively simple standard last-in/first-out non-linear shift register. The sequence inverter must be synchronously timed to the input bit stream, must separately gate out and appropriately delay each bit of the code sequence, and then must linearly add all of the delayed bits. Minimizing the required quantity of sequence inverters for the pulse compressor is therefore very advantageous. However, none would be required at all, if after generating an expanded code a.sub.n and b.sub.n with transposed codes, one of these was then sequence inverted prior to transmission where the sequence inversion could then be achieved with a relatively simple standard LIFO shift register.

Thus what has been shown and described is an improved means for implementing a passive matched filter arrangement which compresses to a lobeless impulse multiplexed noise codes that are expanded with transposed codes of code mate pairs.

Having thus shown and described what is at present considered to be the preferred method and means for embodying the invention, it should be understood that the foregoing detailed description has been made by way of illustration and not limitation. Accordingly, all alterations, modifications and changes coming within the spirit and scope of the invention as set forth in the appended claims are herein meant to be included.

Claims

1. Apparatus for code comprising a mated pair of multiplexed, noise-coded, digital signals (a.sub.i) and (b.sub.i) where the number of bits in each said signal equals 2i comprising:

a plurality of code compressor stages connected in tandem;

each said stage having means for compressing an input mated pair connected thereto into an output mated pair having one-half the number of bits of said input mated pair and having the absolute value of each bit amplitude of said output signal equal to twice the absolute value of each bit amplitude of said input signals;

the first one of said code compressor stages having first and second inputs connected to said input mated pair of signals (a.sub.i) and (b.sub.i) respectively; and

the other of said code compressor stages having first and second inputs connected to first and second outputs respectively of the preceeding one of said stages for connecting said output mated pair thereto.

2. Apparatus according to claim 1 and wherein:

each said stage has said first input therein connected to one input of a first adder and to the input of a first code sequence inverter;

said second input therein connected to one input of a second adder and to the input of a second code sequence inverter;

each said stage having a signal inverter connected between said first code sequence inverter and a second input of said second adder;

said output of said second code sequence inverter connected to a second input of said first adder: and

said first and second outputs of each of said stages connected to the outputs of said first and second adders therein respectively.

3. Apparatus according to claim 1 and wherein:

said first stage has said first input connected to one input of a first adder and the input of a signal inverter;

said second input of said first stage connected to the input of a code sequence inverter;

said code sequence inverter having the output therefor connected to a second input of said first adder and to one input of a second adder;

said signal inverter having the output thereof connected to a second input of said second adder;

the remaining ones of said code compressor stages each having said first input therein connected to a delay means for delaying signals a time period equal to the code length of the signal on said second input therein;

the output of said delay means connected to one input of a first adder and a code inverter therein;

the output of said code inverter connected to one input of a second adder therein;

said second input being connected to a second input of each said first and second adders; and

the outputs of all said first and second adders being connected to said first and second inputs respectively of the succeeding code compressor stage.