Claims
- 1. Apparatus for generating a high voltage, short duration, pulse signal in response to a low level input pulse signal comprising a ground deck driver means transformer-coupled to a floating deck driver means, means for delivering said input pulse to said ground deck drive means, said floating deck driver means serving to generate a first trigger pulse which corresponds to the leading edge of said input pulse and a second trigger pulse which corresponds to the trailing edge of the same, a first FET driver means coupled to the gates of a plurality of series-connected FETs and responsive to said first trigger pulse to enable said series-connected FETs to deliver a high voltage signal to an output load, a second FET driver means coupled to the gates of a second plurality of series-connected FETs and responsive to said second trigger pulse to enable said second plurality of FETs to terminate said high voltage signal, and a third FET driver means also coupled to the gates of the first-mentioned series-connected FETs and responsive to said second trigger pulse to disable said first-mentioned series-connected FETs.
- 2. Apparatus as defined in claim 1 wherein said first-mentioned series-connected FETs are disabled substantially concurrently with the enabling of said second plurality of FETs.
- 3. Apparatus as defined in claim 2 including three transmission line power splitting transformers, each of which serves to couple a respective one of said FET driver means to said series-connected FETs.
- 4. Apparatus as defined in claim 3 wherein said transmission line transformers each comprise a conductive wire mounted in a cylindrical glass tube, and a plurality of toroid cores spaced equidistantly along a length of said tube.
- 5. Apparatus as defined in claim 4 wherein said conductive wire comprises a primary winding and said plurality of toroid cores comprise secondary windings of a transformer, said cores being equal in number to the number of series-connected FETs.
- 6. Apparatus as defined in claim 2 including a shunt discrete capacitance connected from the gate to source of each FET in said series-connected FETs.
- 7. Apparatus as defined in claim 6 including resistance means series connected with said output load for providing predetermined load damping and current limiting.
- 8. Apparatus as defined in claim 7 including means for preventing a false turn-on of the FETs of the first-mentioned series-connected FETs after the same have been disabled.
STATEMENT OF GOVERNMENT RIGHTS
The Government has rights in this invention pursuant to Contract No. DAAK20-83-C-0390 ordered by the Department of the Army.