Patent Application
20240296811
An objective of phase-modulation applications is to minimize the amount of phase ripple. Phase ripple blurs details of an image created by a phase-modulating display and is thus undesirable. This objective is particularly challenging for digitally-driven liquid-crystal displays (LCDs), because in operation these displays can only be written to one of two voltages; a drive voltage that corresponds to fully “on” (or minimum optical retardance) and a relaxation voltage that corresponds to fully “off” (or maximum optical retardance). Actual images require the ability to adjust the optical retardance, and thus the phase shift, over a continuous range between these limits. For digital displays, this is typically done by repeatedly writing a sequence of 1's and O's to a pixel at a rate significantly faster than the rise time or fall time of the liquid crystal element of the pixel. The liquid crystal (LC) element responds to this alternating series of pulses as a root mean squared (RMS) average voltage determined by the duty cycle (i.e., the ratio or comparative relationship of drive voltage times to relaxation voltage times) of the applied voltage pulses.
This rapid alternation technique is capable of accurate phase modulation, but it does exhibit certain limitations. In particular, there is typically some residual ripple in the response of the liquid crystal element due to the rapidly alternating voltage waveform. The magnitude of this ripple is determined by the relationship (e.g., ratio) of the voltage pulse on/off times (i.e., drive voltage and relaxation voltage times) to the liquid crystal element response time. If the liquid crystal element response time is much slower than the on and off times of the voltage across the liquid crystal element, the amount of ripple will be small due to the averaging effect of the relatively slow liquid crystal element response. On the other hand, if the on and off times of the voltage waveform are longer and approach the response time of the liquid crystal element, the liquid crystal element will partially respond to each on and off pulse, and a fairly large optical ripple will result.
Thus, it may be beneficial to provide techniques for driving a phase-modulating display with a voltage waveform that reduces phase ripple.
In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the figure number in which that element is first introduced. Some non-limiting examples are illustrated in the figures of the accompanying drawings in which:
Examples are described herein that provide techniques for controlling a liquid crystal pulse width modulated display. As described above, digital PWM LCDs run the risk of phase ripple when the temporal widths of their pulses (i.e., drive voltage periods) and/or the temporal widths of the periods between pulses (i.e., relaxation voltage periods) is high in relation to the relaxation time of the LC elements of their pixels. However, control schemes for digital LCDs are limited in the number of bits that can be devoted to encoding drive sequences for controlling pulse widths due to allowable size, complexity and power dissipation within the system. Thus, there is a trade-off among three different factors: minimizing the bit length of a drive sequence, achieving a finely-graded scale for pixel grayscale values, and minimizing phase ripple. By evenly distributing pulses of slightly different widths over a time period in which a pixel of the display is driven, examples described herein may provide a binary drive sequence that decreases phase ripple while providing a high degree of grayscale granularity and using a relatively low number of bits in encoding the drive sequence.
As described above, a pixel of a display is driven by a drive sequence of voltage levels, wherein a high voltage level drives the pixel toward the fully “on” state (i.e., minimum retardance, maximum transmittance) and a low voltage drives the pixel toward the fully “off” state (i.e., maximum retardance, minimum transmittance). As used herein, the term “transmittance” refers to the degree to which a liquid crystal element propagates light without retarding it, i.e., transmittance has an inverse relationship to retardance.
As described above, the magnitude of the phase ripple of a phase-modulating display is determined by the relationship (e.g., ratio) of the voltage pulse on/off times (i.e., drive voltage and relaxation voltage times) to the liquid crystal element response time. Thus, to achieve low-ripple phase modulation, it is beneficial to make the alternating voltage pulses happen as quickly as possible, relative to the response time of the liquid-crystal.
It will be appreciated that there are many ways to structure sequences of 1's and 0's that average to the same value. For example, in an 8-bit system, there will be 256 time periods for these pulses to occupy (the elementary time periods of examples described herein are referred to as “unit durations”, which in some examples may correspond to the shortest unit of time encoded by a binary sequence and corresponding to the least significant bit (LSB) of the binary sequence). Suppose that a grayscale value corresponding to an RMS value of 50% of the voltage range is desired, equivalent to 128 unit duration pulses out of a possible 256 unit durations, the grayscale value being encoded as a binary grayscale code value of 127. This grayscale value could be achieved by a voltage sequence of 128 “on” time periods (i.e., 128 unit time periods in which the drive voltage is applied), followed by 128 “off” time periods (i.e., 128 unit duration time periods in which the relaxation voltage is applied). Alternatively, the sequence could consist of 64 unit durations on, 64 off, 64 on, and 64 off. Or the sequence could be (8 on, 8 off) repeated 16 times. At the limit, the sequence could be (1 unit duration on, 1 unit duration off) repeated 128 times. It will be appreciated that the 128 on/128 off case will stay at each voltage for the longest time, resulting in the liquid crystal element having time to respond at least partially to each voltage, and thus resulting in maximum optical ripple at the expense of more toggling activity and hence more dynamic power dissipation. Conversely, the case with 128 repetitions of the 1 on/1 off case will give minimum time for the liquid crystal element to respond to individual voltage pulses, and thus the liquid crystal element will tend to follow the RMS average of the applied voltage, resulting in much lower phase ripple.
It will be appreciated that very low-value and very high-value levels of phase-shift will tend to be problematic in PWM LCD systems. For the 8-bit system having repetition periods of 255 unit durations (e.g., an 8-bit encoding representing grayscale values between 0 and 255), a desired modulation code (e.g., binary grayscale code) of “2” would require a pulse sequence that in total was at the drive voltage for only 2 unit durations and was at relaxation voltage for the other 253 unit durations. Likewise, a desired modulation code of “253” would require a pulse sequence that in total was at drive voltage for 253 of the unit durations, and only at relaxation voltage for 2 unit durations. These cases are inherently very irregular, and in these cases the best that can be done is typically to spread out the modulation pulses as evenly as possible. In fact, this is a general objective in many types of pulse sequence: the distribution of on and off pulses must be as even as possible during each sequence in order to achieve the lowest possible ripple.
As described above, however, there are typically conflicting requirements and trade-offs among different designs. Driving very fast pulse sequences to large arrays of pixels (such as are common in modern displays) can be electrically very challenging due to the extremely high data rates required. For example, a high-definition (HD) display will typically have about 2.2 million pixels, and writing a potentially different sequence of 1's and O's to each of these pixels many times in a row (as in the above “1 on/1 off” case shown in
Examples described herein, in reference to
In some examples, a mixed-mode method can be used to generate the drive sequence for the pixel. In some examples, the drive sequence controls the transmittance of the liquid crystal of a pixel over the time in which the display shows a frame or, in the case of color sequential displays, a color sub-frame (called the “frame time”). Modern LCDs display frames at a refresh rate or frame rate of many frames per second, such as 30 Hz or 120 Hz. In color sequential displays, each frame may be displayed as a sequence of color sub-frames, such as three color sub-frames per frame (e.g., a 360 Hz color sub-frame rate (CSFR) for a RGB display at a frame rate of 120 Hz). The drive sequence is configured to maintain the desired grayscale value of the pixel over the frame time, e.g., either a grayscale value for the pixel as a whole over the duration of the entire frame, or a color-specific grayscale value over the duration of the color sub-frame for the specific color.
In the examples illustrated in
By converting a grayscale value into a large number of relatively short-width pulses and reducing the variation between pulse widths, drive sequences generated according to some examples described herein may address the technical problem of reducing phase ripple in the image generated by the pixels of a PWM display, such as a PWM LCD, while also addressing the technical problem of encoding and decoding the large number of short-width pulses according to a simple 10-bit encoding and decoding scheme. This may improve the functioning of a display, such as a LCD, as well as improving the functioning of a computer or other digital logic driving the display, by enabling simple, low-complexity encoding and decoding of the drive sequence for each pixel while reducing phase ripple of the image generated by the display.
It will be appreciated that some examples may use a different number of group periods, a different number of modulation intervals, a different modulation interval duration, a different distribution of remainder bits, and/or a different bit encoding than the examples described herein while still potentially realizing one or more such benefits. For example, an alternative 10-bit encoding for the repetition period of the drive sequence could be used in some examples to encode a repetition period having 16 group periods, each having 4 modulation periods of 16 unit durations each (15 unit durations for the final modulation interval of the final group period).
Because each pulse train (driven over a modulation interval) has a width that differs from each other pulse train by at most 1 unit duration, the drive sequence has a short-term RMS voltage as close to being constant as is possible for a given unit duration. At the highest code values (e.g., grayscale value of 1020 out of a possible 1023), these durations will begin to merge with each other, giving the appearance of being longer pulses. This is unavoidable if the total available duration is to be utilized. At the limit, for a grayscale value of 1023, all of the pulses merge and the voltage is continuously high. Likewise, at a grayscale value of 0, the voltage value will be continuously low, as would be expected.
As noted above, the structure of the drive sequence for the repetition period is that of 16 repetitions of a group period, each group period encompassing a group of 8 modulation intervals. The pulses corresponding to the modulation intervals all have the same duration of 0 to 7 unit durations (called the main segment pulse duration, denoted H herein), plus in some cases a single additional “remainder” pulse of one unit duration. Determining the value of H and the distribution of remainder pulses may be performed, in some examples, according to a method 300 shown in the flowchart of
According to some examples, the method includes receiving a grayscale value between a grayscale minimum and a grayscale maximum at operation 302. The grayscale value may be on any scale, such as an integer from 0 to 255, or a real number value (e.g., represented as a floating point number encoding).
According to some examples, the method includes transforming the grayscale value into a number N representing the desired number of unit duration pulses in a repetition period of the drive sequence at operation 304. As described above, the repetition period consists of a first number A of group periods (e.g., A=16 in the illustrated examples), each group period consisting of a second number B of modulation intervals (e.g., B=8 in the illustrated examples), and each modulation interval comprising a third number (C−1) of unit durations (e.g., C=8 in the illustrated examples), followed by, for each modulation interval except a final modulation interval of a final group period, an additional unit duration, such that the repetition period spans ((A×B×C)−1) unit durations. A detailed illustration of this structure is shown in
The transformation of operation 304 is essentially a normalization of the grayscale value to the number of unit durations in the repetition period: thus, the output of this operation 304 is N=0 at the grayscale minimum, and N=(A×B×C)−1 at grayscale maximum. Thus, for example, in an example in which a repetition period spans 1023 unit durations, and N ranges from 0 to 1023, and in which A=16, B=8, and C=8, the grayscale value is normalized at operation 304 to a value between N=0 and N=1023.
According to some examples, the method includes determining a group period baseline number of pulses D equal to the integer quotient of the Euclidean division of N by A at operation 306. Thus, in the example above, if the normalized grayscale code results in a value of N=666, then D=N div A=666 div 16=41.
According to some examples, the method includes determining a modulation interval baseline number of pulses H equal to the integer quotient of the Euclidean division of D by B at operation 308. Thus, in the example above, H=D div B=41 div 8=5 remainder 1.
According to some examples, the method includes determining a main segment modulation interval pattern consisting of H unit duration pulses at the first H unit durations of each modulation interval at operation 310. Thus, in the example above, each 8-unit duration modulation interval beings with a main segment pulse of 5 unit durations. This may be followed by a relaxation voltage period of 3 unit durations, or, if a remainder pulse is added to this modulation period, a single additional unit duration pulse followed by a relaxation voltage period of 2 unit durations.
According to some examples, the method includes determining a repetition period remainder L2 equal to the integer remainder of the Euclidean division of N by A, and determining a group period remainder L equal to the integer remainder of the Euclidean division of D by B, at operation 312. Thus, in the example above, L2=N rem A=666 rem 16=10, and L=D rem B=41 rem 8=1.
It will be appreciated that, in some examples, the values of D, H, L and/or L2 can be determined at operations 306, 308, 310, and 312 using a relatively simply binary mapping operation, such as the example binary mapping shown in
According to some examples, the method includes determining a baseline group period pattern at operation 314. The baseline group period pattern consists of the main segment modulation interval pattern applied to each modulation interval of the group period, and an additional L unit duration pulses allocated to a unit duration following the first H unit durations of each of L modulation intervals selected from the group period.
In some examples, the L modulation intervals are selected at operation 314 using a rule or lookup table that evenly distributes the L remainder pulses over a group period. An example of a lookup table for a case in which B=8 is shown below. The L modulation intervals selected from the eight sequential modulation intervals of each group period are shown in the lookup table:
It will be appreciated from the L remainder lookup table above that an L remainder pulse is never added to the last (e.g., eighth) modulation interval of a group period. The final unit duration of the final modulation interval of each group period is reserved for handling the L2 remainder pulses, at operation 316 below.
According to some examples, the method includes determining a repetition sequence for the repetition period at operation 316. The repetition sequence consists of the baseline group period pattern repeated for each group period of the repetition period, and an additional L2 unit duration pulses allocated to a unit duration following the first H unit durations of a final modulation interval of each of L2 group periods selected from the repetition period.
In some examples, as with operation 314, the L2 modulation intervals are selected at operation 316 using a rule or lookup table that evenly distributes the L remainder pulses over a group period. An example of a lookup table for a case in which A=16 is shown below. The L2 group periods selected from the sixteen sequential group periods of the repetition period are shown in the lookup table below:
It will be appreciated from the L2 lookup table above that no remainder is ever added to the final (e.g., eighth) modulation interval of the final (e.g., 16th) group period. In the example 10-bit encoding illustrated in the figures, this final unit duration of the repetition period is omitted from the repetition sequence, and the next repetition period begins immediately, although in some examples this final bit of the repetition sequence could be used to achieve higher bit-depths or for other purposes. However, in the examples illustrated herein, the omission of this final bit means that the 10-bit encoding of the repetition sequence can encode at most (210−1)=1023 unit durations of drive voltage (i.e., a unit duration pulse) or relaxation voltage (i.e., absence of a pulse).
Thus, in the ongoing example in which a repetition period spans 1023 unit durations, A=16, B=8, C=8, and N=666, the pulse widths for each pulse train of a given modulation interval can be computed as follows:
According to some examples, the method includes generating a drive sequence for controlling the liquid crystal pulse width modulated display, the drive sequence comprising the repetition sequence repeated one or more times at operation 318.
For code values less than the maximum grayscale value (e.g., less than 1023 in the 10-bit example described above), example method 300 described above may not be maximally efficient at the temporal beginning of a frame to be displayed on the display, because the LC must be brought as quickly as possible to the approximate desired phase value, and this may require 100% duty-cycle on-time (i.e., 100% of time spent at drive voltage) until the desired phase value is reached (assuming that the LC element starts the frame time at a transmittance value of 0). To address this further technical problem, some examples may include a relatively long duration of continuous drive voltage at the beginning of a frame (or sub-frame, as the case may be). This continuous drive voltage is referred to as a pre-emphasis pulse (or a pre-emphasis period or overdrive period). The use of a pre-emphasis period is analogous to techniques used in high-speed digital signal transmission.
Thus, in some examples, the drive sequence further comprises, prior to the repetition sequence repeated one or more times, a pre-emphasis period of continuous drive (e.g., drive voltage).
In some examples, the pre-emphasis period is of a different duration depending on the grayscale value—in general, the higher the desired grayscale value, the longer the pre-emphasis period will need to be. Determining the optimum duration of a pre-emphasis period may be an empirical process, and may be temperature-dependent in some examples. Thus, in some examples, the pre-emphasis period has a duration determined based at least in part on a temperature of the liquid crystal pulse width modulated display.
Once the end of the pre-emphasis period is reached, control of the display may switch to the method 300 outlined above, and the pre-emphasis period may not be repeated until the next image frame or color sub-frame begins.
The bit mapping scheme also includes an overdrive mapping table 410 for mapping the values of the most significant bits (bits 7 to 9 (404) corresponding to the main segment value 414 H, and bits 4 to 6 (406) corresponding to L remainder value (416)) to an overdrive value 412 indicating the duration of the pre-emphasis period. The overdrive value 412 is encoded on the DATA bus as DATA bits 21 to 26 (426). Thus, in the illustrated example, the most significant bits of the 10-bit phase value 402 are used to determine the necessary duration of pre-emphasis, a principle described in greater detail with reference to
In this example, the group period 526 begins with the first modulation interval 524, in which a first modulation interval pattern 522 begins with a main segment pulse of H unit durations 528, followed by a pulse in the remainder unit duration (due to the L lookup table allocating the one remainder pulse L=1 to the first modulation interval of each group period). The final five unit durations of the first modulation interval 524 are at relaxation voltage. Modulation intervals 2 through 7 (including the identified example of the third modulation interval 540) each has a main segment pulse of two unit durations, with no allocated remainder pulse. The eighth modulation interval 544, ending at the end of group period 536, begins with a pulse of H unit durations 532 followed by a pulse during the remainder unit duration 534. The subsequent group period begins with a modulation interval identical to the first modulation group period 526, with an L remainder pulse remainder unit duration 538 allocated thereto.
In this example, the group period 548 begins with the first modulation interval 542, in which a first modulation interval pattern 546 has a zero-width main segment pulse because H=0. Instead, the first modulation interval 542 begins with a pulse in the remainder unit duration 550. The final seven unit durations of the first modulation interval 542 are at relaxation voltage. Modulation intervals 2 through 7 each has a main segment pulse of zero unit durations, with no allocated remainder pulse. The eighth modulation interval 556, ending at the end of group period 554, begins with a pulse during the remainder unit duration 552. The subsequent group period begins with a modulation interval identical to the first modulation group period first modulation interval 542, beginning with an L remainder pulse remainder unit duration allocated thereto.
It will be appreciated that these described examples adhere to a number of rules:
It will be appreciated that these described examples adhere to a number of additional rules:
A detailed expanded view of second group period 714 is shown in the second row. A first modulation interval 718 of second group period 714 follows the end of first group period 716. The final unit duration of first modulation interval 718 is an L remainder unit duration 722. The eighth modulation interval 720 ends with an L2 remainder unit duration 724 instead, because it is the last modulation interval in the group period.
Detailed expanded views of first modulation interval 718 and eighth modulation interval 720 are shown in the third row. After the end of first group period 716, the first modulation interval 718 begins with first unit duration 726, and it ends with the L remainder unit duration 722. The L remainder unit duration 722 begins with first unit duration 730 and ends with L2 remainder unit duration 724.
It will be appreciated that this drive sequence represents a relatively high grayscale value in which H=C−1, because the L and L2 remainder slots are at the final unit duration position in each modulation interval (as in
During the pre-emphasis period 802, the LC transmittance 814 increases in accordance with a linear ramp 804 as 100% drive voltage is applied. During the repetition period 806, a steady-state 808 grayscale value is maintained, in accordance with method 300 described above. During the relaxation period 810, in preparation for the next frame or sub-frame, the LC exhibits LC relaxation 812 during a period of 100% relaxation voltage.
As shown, the pixel circuit 1000 includes a pixel electrode 1036 containing a mirror element to reflect incoming light and drive a time-varying voltage across a liquid crystal element between the pixel electrode 1036 and the common electrode 1038 on the cover glass of the display. A level shifter circuit 1044 converts internal logic voltages to a higher voltage suitable for driving the liquid crystal element, and may in some examples contain an XOR logic function for inverting the sense of the pixel electrode 1036 when inverting the sense of the common electrode 1038 voltage as controlled by the FLIP signal 1032. A flip-flop 1024 stores and holds the pixel electrode 1036 voltage value for one cycle of the GSET signal 1030. The flip-flop 1024 may be reset by the RESET signal 1034. An OD-ON latch 1026 stores the ON/OFF state 1042 of an overdrive function. A first multiplexer 1028 is controlled by the output of the OD-ON latch 1026 to select between an ODC signal carried on the overdrive count (ODC) bus 1002 and a global (G) signal carried on the global counter (G) bus 1004 as a first operand of a comparator function 1022. A second multiplexer 1020 is controlled by the SEL signal 1006 to select the second operand of the comparator function 1022. A series of storage latches, shown as overdrive latches 1012, main segment latches 1014, L remainder latches 1016, and L2 remainder latches 1018, cache encoded binary values representing the drive sequence, which are propagated to drive the pixel electrode 1036. The bit lengths and bit positions shown in
During the pre-emphasis period 1110, the operation of the pixel circuit 1000 proceeds as follows: data to be written to the storage latches 1012, 1014, 1016, 1018 is provided on the DATA bus 1010, and the ROW signal 1008 is strobed to write the DATA bus 1010 values to the storage latches 1012, 1014, 1016, 1018. The RESET signal 1034 is pulsed to set the pixel electrode 1036 voltage value high, and also to set the OD-ON latch 1026 to put the pixel circuit 1000 into overdrive mode. The GSET signal 1030 begins toggling to act as a clock signal for the flip-flop 1024. During the subsequent pre-emphasis period, the ODC bus signal 1116 is being compared to the value in the overdrive latches 1012, and when the values are equal, the comparator function 1022 registers a match, which is clocked into the flip-flop 1024. When the output of the flip-flop 1024 changes, the OD-ON latch 1026 will be reset, and the first multiplexer 1028 will select the G bus 1004 as the first operand for the comparator function 1022 henceforth. This marks the end of the pre-emphasis period and the beginning of the first repetition period for maintaining the steady-state grayscale value.
Thus, the ODC bus signal 1116 is considered a timer signal for the overdrive state, and is compared to the values of the overdrive latches 1012 to determine the ending time of the pre-emphasis period. In the illustrated example, the ODC bus signal 1116 encodes a duration of the pre-emphasis period from 0 to 63 group periods, and each G/SEL waveform period (e.g., 1118) corresponds to a repetition period. Thus, the 64 group periods over which the pre-emphasis period can extend (0 to 63) correspond to the first repetition period 1118 through a fourth repetition period 1120. However, it will be appreciated that the range of durations of the pre-emphasis period encoded in the OD bits stored in the overdrive latches 1012 can be configured in various examples to cover any suitable range of durations based on factors such as the properties of the liquid crystal element.
As described above, before or at the beginning of the pre-emphasis period (e.g., during the load period 1108), the data to be written to the storage latches 1012, 1014, 1016, 1018 is provided on the DATA bus 1010, and the ROW signal 1008 is strobed to write the DATA bus 1010 values to the storage latches 1012, 1014, 1016, 1018. Thus, as shown in
During the repetition periods spanning the steady-state illumination period 1112, different iterations of the repetition period will be realized, according to the previously described method 300. During the main segment 1138 pulses of each modulation interval, the main segment latches 1014 are selected as the first operand of the comparator function 1022 along with the global signal 1136 carried by the G bus 1004 as the second operand. Global signal 1136 values are periodically updated, and the GSET signal 1030 is pulsed to clock in the comparator function 1022 output. When the comparator function 1022 sees a match between the G bus 1004 and the storage latch 1012, 1014, 1016, 1018 values, the output state of the comparator function 1022 changes, thereby forming the width of the pulse of the modulation interval. During each of the remainder unit durations 1140, the SEL signal 1006 determines which latch or latches are used as operands (e.g., according to the values shown on the first multiplexer 1028 in
As described above, examples described herein may address one or more technical problems associated with pulse width modulated displays. By converting a grayscale value into a large number of relatively short-width pulses and reducing the variation between pulse widths, some examples described herein may address the technical problem of reducing phase ripple in the image generated by the pixels of a PWM display, such as a PWM LCD, while also addressing the technical problem of encoding and decoding the large number of short-width pulses according to a simple 10-bit encoding and decoding scheme. This may improve the functioning of a display, such as a LCD, as well as improving the functioning of a computer or other digital logic driving the display, by enabling simple, low-complexity encoding and decoding of the drive sequence for each pixel while reducing phase ripple of the image generated by the display.
Furthermore, some examples may attempt to address the technical problem of bringing the liquid crystal element of a pixel to the steady-state phase value as quickly as possible at the beginning of a frame or sub-frame, by providing a pre-emphasis period at the beginning of a drive sequence. Some examples herein may encode the pre-emphasis period in a binary format efficiently decodable by pixel circuitry or other logic used to drive the voltage of a LC element of a pixel.
Thus, in accordance with examples described herein, a method and system may be provided for controlling a liquid crystal pulse width modulated display.
In a first aspect, a method for controlling a liquid crystal pulse width modulated display is provided. The method includes determining a desired number N of pulses of a unit duration over a repetition period, the repetition period consisting of a first number A of group periods, each group period consisting of a second number B of modulation intervals, and each modulation interval includes a third number (C−1) of unit durations followed by, for each modulation interval except a final modulation interval of a final group period, an additional unit duration. The method also includes such that the repetition period spans (A×B×C)−1 unit durations. The method also includes determining a group period baseline number of pulses D equal to the integer quotient of the Euclidean division of N by A. The method also includes determining a modulation interval baseline number of pulses H equal to the integer quotient of the Euclidean division of D by B. The method also includes determining a main segment modulation interval pattern consisting of H unit duration pulses at the first H unit durations of each modulation interval. The method also includes determining a repetition period remainder L2 equal to the integer remainder of the Euclidean division of N by A. The method also includes determining a group period remainder L equal to the integer remainder of the Euclidean division of D by B. The method also includes determining a baseline group period pattern consisting of the main segment modulation interval pattern applied to each modulation interval of the group period, and an additional L unit duration pulses allocated to a unit duration following the first H unit durations of each of L modulation intervals selected from the group period. The method also includes determining a repetition sequence for the repetition period consisting of the baseline group period pattern repeated for each group period of the repetition period, and an additional L2 unit duration pulses allocated to a unit duration following the first H unit durations of a final modulation interval of each of L2 group periods selected from the repetition period. The method also includes determining a desired number N of pulses of a unit duration over a repetition period, the repetition period consisting of determining a baseline group period pattern consisting of generating a drive sequence for controlling the liquid crystal pulse width modulated display, the drive sequence includes the repetition sequence repeated one or more times.
In some examples, the method may also include, in combination with the first aspect above, where the drive sequence further includes, prior to the repetition sequence repeated one or more times a pre-emphasis period of continuous drive.
In some examples, the method may also include, in combination with the first aspect and optionally with one or more of the examples above, where the unit duration is a least significant bit (LSB) duration.
In some examples, the method may also include, in combination with the first aspect and optionally with one or more of the examples above, where determining the desired number N of unit duration pulses over the repetition period includes receiving a grayscale value between a grayscale minimum and a grayscale maximum, and transforming the grayscale value into the desired number N, where a value of N=0 corresponds to the grayscale minimum and a value of N=(A×B×C)−1 corresponds to the grayscale maximum.
In some examples, the method may also include, in combination with the first aspect and optionally with one or more of the examples above, where A is 16, B is 8, C is 8, and N is encoded as a 10-bit value. Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.
In some examples, the method may also include, in combination with the first aspect and optionally with one or more of the examples above, where the pre-emphasis period has a duration determined based at least in part on a temperature of the liquid crystal pulse width modulated display.
In some examples, the method may also include, in combination with the first aspect and optionally with one or more of the examples above, where the L modulation intervals selected from the eight sequential modulation intervals of the group period are the first modulation interval when L is 1, the first and fifth modulation intervals when L is 2, the first, fourth, and seventh modulation intervals when L is 3, the first, third, fifth, and seventh modulation intervals when L is 4, the first, second, fourth, fifth, and seventh modulation intervals when L is 5, the first, second, third, fifth, sixth, and seventh modulation intervals when L is 6, and the first, second, third, fourth, fifth, sixth, and seventh modulation intervals when L is 7.
In some examples, the method may also include, in combination with the first aspect and optionally with one or more of the examples above, where the L2 group periods selected from the 16 sequential group periods of the repetition period are the first group period when L2 is 1, the first and ninth group periods when L2 is 2, the first, sixth, and ninth group periods when L2 is 3, the first, fourth, eighth, and twelfth group periods when L2 is 4, the first, fourth, eighth, eleventh, and fourteenth group periods when L2 is 5, the first, fourth, seventh, ninth, twelfth, and fifteenth group periods when L2 is 6, the first, third, fifth, eighth, tenth, twelfth, and fourteenth group periods when L2 is 7, the first, third, fifth, seventh, ninth, eleventh, thirteenth, and fifteenth group periods when L2 is 8, the first, third, fourth, sixth, eighth, tenth, twelfth, thirteenth, fifteenth group periods when L2 is 9, the first, third, fourth, sixth, eighth, ninth, eleventh, twelfth, thirteenth, fifteenth group periods when L2 is 10, the first, second, fourth, fifth, sixth, eighth, ninth, eleventh, twelfth, thirteenth, fifteenth group periods when L2 is 11, the first, second, third, fifth, sixth, seventh, ninth, tenth, eleventh, twelfth, fourteenth, fifteenth group periods when L2 is 12, the first, second, third, fourth, sixth, seventh, eighth, ninth, tenth, twelfth, thirteenth, fourteenth, fifteenth group periods when L2 is 13, the first, second, third, fourth, fifth, sixth, seventh, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth group periods when L2 is 14, and the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth group periods when L2 is 15.
In some examples, the method may also include, in combination with the first aspect and optionally with one or more of the examples above, further includes driving a pixel of the liquid crystal pulse width modulated display with the drive sequence, where the pixel includes one or more latches operable to store binary values of the drive sequence, where the drive sequence encodes the pre-emphasis period as a binary overdrive duration value. The method may also include where the pixel includes a pixel electrode includes a mirror element to reflect incoming light and drive a time-varying voltage across a liquid crystal element between the pixel electrode and a common electrode. The method may also include where the pixel includes a level shifter circuit configured to convert internal logic voltages to a higher voltage suitable for driving the liquid crystal element. The method may also include where the pixel includes logic operable to receive one or more timer signals and, based on the one or more timer signals during the pre-emphasis period, determined based on a comparison of the one or more timer signals to the binary overdrive duration value, provide an overdrive signal to the level shifter circuit, during each main segment modulation interval pattern of the drive sequence, provide a drive signal to the level shifter circuit, during each additional L unit duration pulse of the drive sequence, provide a drive signal to the level shifter circuit, and during each additional L2 unit duration pulse of the drive sequence, provide a drive signal to the level shifter circuit.
In some examples, the method may also include, in combination with the first aspect and optionally with one or more of the examples above, where the level shifter circuit includes an XOR logic function configured to invert a sense of the pixel electrode when inverting a sense of the common electrode voltage as controlled by a FLIP signal.
In a second aspect, a system for controlling a liquid crystal pulse width modulated display is provided, including a drive sequence generator configured to perform operations including receiving normalized grayscale data representative of a desired number N of unit duration pulses over a repetition period, the repetition period consisting of a first number A of group periods, each group period consisting of a second number B of modulation intervals, and each modulation interval includes a third number (C−1) of unit durations followed by, for each modulation interval except a final modulation interval of a final group period, an additional unit duration. The system also includes such that the repetition period spans (A×B×C)−1 unit durations. The system also includes determining a group period baseline number of pulses D equal to the integer quotient of the Euclidean division of N by A. The system also includes determining a modulation interval baseline number of pulses H equal to the integer quotient of the Euclidean division of D by B. The system also includes determining a main segment modulation interval pattern consisting of H unit duration pulses at the first H unit durations of each modulation interval. The system also includes determining a repetition period remainder L2 equal to the integer remainder of the Euclidean division of N by A. The system also includes determining a group period remainder L equal to the integer remainder of the Euclidean division of D by B. The system also includes determining a baseline group period pattern consisting of the main segment modulation interval pattern applied to each modulation interval of the group period, and an additional L unit duration pulses allocated to a unit duration following the first H unit durations of each of L modulation intervals selected from the group period. The system also includes determining a repetition sequence for the repetition period consisting of the baseline group period pattern repeated for each group period of the repetition period, and an additional L2 unit duration pulses allocated to a unit duration following the first H unit durations of a final modulation interval of each of L2 group periods selected from the repetition period. The system also includes receiving normalized grayscale data representative of a desired number N of unit duration pulses over a repetition period, the repetition period consisting of determining a baseline group period pattern consisting of generating a drive sequence for controlling the liquid crystal pulse width modulated display, the drive sequence includes the repetition sequence repeated one or more times.
In some examples, the system may also include, in combination with the second aspect above, a pre-emphasis driver configured to provide, prior to the repetition sequence repeated one or more times, a pre-emphasis period of continuous drive.
In some examples, the system may also include, in combination with the second aspect and optionally with one or more of the examples above, where the unit duration is a least significant bit (LSB) duration.
In some examples, the system may also include, in combination with the second aspect and optionally with one or more of the examples above, a grayscale normalizer configured to receive a grayscale value between a grayscale minimum and a grayscale maximum, and transforming the grayscale value into the desired number N, where a value of N=0 corresponds to the grayscale minimum and a value of N=(A×B×C)−1 corresponds to the grayscale maximum.
In some examples, the system may also include, in combination with the second aspect and optionally with one or more of the examples above, where A is 16, B is 8, C is 8, and N is encoded as a 10-bit value.
In some examples, the system may also include, in combination with the second aspect and optionally with one or more of the examples above, a pixel driver to drive a pixel of the liquid crystal pulse width modulated display with the drive sequence. The system may also include the pixel, includes one or more latches operable to store binary values of the drive sequence, where the drive sequence encodes the pre-emphasis period as a binary overdrive duration value. The system may also include the pixel, includes a pixel electrode includes a mirror element to reflect incoming light and drive a time-varying voltage across a liquid crystal element between the pixel electrode and a common electrode. The system may also include the pixel, includes a level shifter circuit configured to convert internal logic voltages to a higher voltage suitable for driving the liquid crystal element. The system may also include the pixel, includes logic operable to receive one or more timer signals and, based on the one or more timer signals during the pre-emphasis period, determined based on a comparison of the one or more timer signals to the binary overdrive duration value, provide an overdrive signal to the level shifter circuit, during each main segment modulation interval pattern of the drive sequence, provide a drive signal to the level shifter circuit, during each additional L unit duration pulse of the drive sequence, provide a drive signal to the level shifter circuit, and during each additional L2 unit duration pulse of the drive sequence, provide a drive signal to the level shifter circuit. Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.
In some examples, the system may also include, in combination with the second aspect and optionally with one or more of the examples above, where the pre-emphasis period has a duration determined based at least in part on a temperature of the liquid crystal pulse width modulated display.
In some examples, the system may also include, in combination with the second aspect and optionally with one or more of the examples above, where the L modulation intervals selected from the eight sequential modulation intervals of the group period are the first modulation interval when L is 1, the first and fifth modulation intervals when L is 2, the first, fourth, and seventh modulation intervals when L is 3, the first, third, fifth, and seventh modulation intervals when L is 4, the first, second, fourth, fifth, and seventh modulation intervals when L is 5, the first, second, third, fifth, sixth, and seventh modulation intervals when L is 6, and the first, second, third, fourth, fifth, sixth, and seventh modulation intervals when L is 7.
In some examples, the system may also include, in combination with the second aspect and optionally with one or more of the examples above, where the L2 group periods selected from the 16 sequential group periods of the repetition period are the first group period when L2 is 1, the first and ninth group periods when L2 is 2, the first, sixth, and ninth group periods when L2 is 3, the first, fourth, eighth, and twelfth group periods when L2 is 4, the first, fourth, eighth, eleventh, and fourteenth group periods when L2 is 5, the first, fourth, seventh, ninth, twelfth, and fifteenth group periods when L2 is 6, the first, third, fifth, eighth, tenth, twelfth, and fourteenth group periods when L2 is 7, the first, third, fifth, seventh, ninth, eleventh, thirteenth, and fifteenth group periods when L2 is 8, the first, third, fourth, sixth, eighth, tenth, twelfth, thirteenth, fifteenth group periods when L2 is 9, the first, third, fourth, sixth, eighth, ninth, eleventh, twelfth, thirteenth, fifteenth group periods when L2 is 10, the first, second, fourth, fifth, sixth, eighth, ninth, eleventh, twelfth, thirteenth, fifteenth group periods when L2 is 11, the first, second, third, fifth, sixth, seventh, ninth, tenth, eleventh, twelfth, fourteenth, fifteenth group periods when L2 is 12, the first, second, third, fourth, sixth, seventh, eighth, ninth, tenth, twelfth, thirteenth, fourteenth, fifteenth group periods when L2 is 13, the first, second, third, fourth, fifth, sixth, seventh, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth group periods when L2 is 14, and the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth group periods when L2 is 15.
In some examples, the system may also include, in combination with the second aspect and optionally with one or more of the examples above, where the level shifter circuit includes an XOR logic function configured to invert a sense of the pixel electrode when inverting a sense of the common electrode voltage as controlled by a FLIP signal. Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.
It will be appreciated that the various aspects of the methods and systems described above may be combined in various combination or sub-combinations.
“Euclidean division” or “division with remainder” refers to a process of dividing an integer dividend by an integer divisor to produce an integer quotient and a natural number remainder, the remainder being smaller than the divisor, and the dividend being equal to the divisor times the quotient, plus the remainder.
“Component” refers, for example, to a device, physical entity, or logic having boundaries defined by function or subroutine calls, branch points, APIs, or other technologies that provide for the partitioning or modularization of particular processing or control functions. Components may be combined via their interfaces with other components to carry out a machine process. A component may be a packaged functional hardware unit designed for use with other components and a part of a program that usually performs a particular function of related functions. Components may constitute either software components (e.g., code embodied on a machine-readable medium) or hardware components. A “hardware component” is a tangible unit capable of performing certain operations and may be configured or arranged in a certain physical manner. In various examples, one or more computer systems (e.g., a standalone computer system, a client computer system, or a server computer system) or one or more hardware components of a computer system (e.g., a processor or a group of processors) may be configured by software (e.g., an application or application portion) as a hardware component that operates to perform certain operations as described herein. A hardware component may also be implemented mechanically, electronically, or any suitable combination thereof. For example, a hardware component may include dedicated circuitry or logic that is permanently configured to perform certain operations. A hardware component may be a special-purpose processor, such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). A hardware component may also include programmable logic or circuitry that is temporarily configured by software to perform certain operations. For example, a hardware component may include software executed by a general-purpose processor or other programmable processors. Once configured by such software, hardware components become specific machines (or specific components of a machine) uniquely tailored to perform the configured functions and are no longer general-purpose processors. It will be appreciated that the decision to implement a hardware component mechanically, in dedicated and permanently configured circuitry, or in temporarily configured circuitry (e.g., configured by software), may be driven by cost and time considerations. Accordingly, the phrase “hardware component” (or “hardware-implemented component”) should be understood to encompass a tangible entity, be that an entity that is physically constructed, permanently configured (e.g., hardwired), or temporarily configured (e.g., programmed) to operate in a certain manner or to perform certain operations described herein. Considering examples in which hardware components are temporarily configured (e.g., programmed), each of the hardware components need not be configured or instantiated at any one instance in time. For example, where a hardware component comprises a general-purpose processor configured by software to become a special-purpose processor, the general-purpose processor may be configured as respectively different special-purpose processors (e.g., comprising different hardware components) at different times. Software accordingly configures a particular processor or processors, for example, to constitute a particular hardware component at one instance of time and to constitute a different hardware component at a different instance of time. Hardware components can provide information to, and receive information from, other hardware components. Accordingly, the described hardware components may be regarded as being communicatively coupled. Where multiple hardware components exist contemporaneously, communications may be achieved through signal transmission (e.g., over appropriate circuits and buses) between or among two or more of the hardware components. In examples in which multiple hardware components are configured or instantiated at different times, communications between such hardware components may be achieved, for example, through the storage and retrieval of information in memory structures to which the multiple hardware components have access. For example, one hardware component may perform an operation and store the output of that operation in a memory device to which it is communicatively coupled. A further hardware component may then, at a later time, access the memory device to retrieve and process the stored output. Hardware components may also initiate communications with input or output devices, and can operate on a resource (e.g., a collection of information). The various operations of example methods described herein may be performed, at least partially, by one or more processors that are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, such processors may constitute processor-implemented components that operate to perform one or more operations or functions described herein. As used herein, “processor-implemented component” refers to a hardware component implemented using one or more processors. Similarly, the methods described herein may be at least partially processor-implemented, with a particular processor or processors being an example of hardware. For example, at least some of the operations of a method may be performed by one or more processors or processor-implemented components. Moreover, the one or more processors may also operate to support performance of the relevant operations in a “cloud computing” environment or as a “software as a service” (SaaS). For example, at least some of the operations may be performed by a group of computers (as examples of machines including processors), with these operations being accessible via a network (e.g., the Internet) and via one or more appropriate interfaces (e.g., an API). The performance of certain of the operations may be distributed among the processors, not only residing within a single machine, but deployed across a number of machines. In some examples, the processors or processor-implemented components may be located in a single geographic location (e.g., within a home environment, an office environment, or a server farm). In other examples, the processors or processor-implemented components may be distributed across a number of geographic locations.
“Computer-readable storage medium” refers, for example, to both machine-storage media and transmission media. Thus, the terms include both storage devices/media and carrier waves/modulated data signals. The terms “machine-readable medium,” “computer-readable medium” and “device-readable medium” mean the same thing and may be used interchangeably in this disclosure.
“Machine storage medium” refers, for example, to a single or multiple storage devices and media (e.g., a centralized or distributed database, and associated caches and servers) that store executable instructions, routines and data. The term shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media, including memory internal or external to processors. Specific examples of machine-storage media, computer-storage media and device-storage media include non-volatile memory, including by way of example semiconductor memory devices, e.g., erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), FPGA, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks The terms “machine-storage medium,” “device-storage medium,” “computer-storage medium” mean the same thing and may be used interchangeably in this disclosure. The terms “machine-storage media,” “computer-storage media,” and “device-storage media” specifically exclude carrier waves, modulated data signals, and other such media, at least some of which are covered under the term “signal medium.”
“Non-transitory computer-readable storage medium” refers, for example, to a tangible medium that is capable of storing, encoding, or carrying the instructions for execution by a machine.
“Signal medium” refers, for example, to any intangible medium that is capable of storing, encoding, or carrying the instructions for execution by a machine and includes digital or analog communications signals or other intangible media to facilitate communication of software or data. The term “signal medium” shall be taken to include any form of a modulated data signal, carrier wave, and so forth. The term “modulated data signal” means a signal that has one or more of its characteristics set or changed in such a matter as to encode information in the signal. The terms “transmission medium” and “signal medium” mean the same thing and may be used interchangeably in this disclosure.
This patent application claims the benefit of U.S. Provisional Patent Application No. 63/487,795, filed Mar. 1, 2023, entitled “PULSE WIDTH MODULATION FOR PHASE-MODULATING DISPLAY”, which is incorporated by reference herein in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63487795 | Mar 2023 | US |
