Patent Application
20050128777
The present invention relates to an inverter servo drive which drives a motor at variable speeds and to a PWM inverter which interconnects systems.
In relation to a PWM inverter which outputs an arbitrary sinusoidal voltage by means of activation/deactivation of an IGBT or the like, there are proposed some signal generating methods for a PWM pulse signal which can serve as a command to activate/deactivate an IGBT or the like. One is a method such as illustrated in
However, a maximum line voltage (amplitude value) which can be output under the space vector PWM method coincides with a direct current bus voltage of the PWM inverter. In both of these methods, a maximum output line voltage assumes a sinusoidal waveform.
However, some applications require a larger output voltage, wherein a line output voltage does not necessarily assume a sinusoidal waveform.
A first related art example includes a method for outputting a six-step voltage (a(1) through a(3), and b(1) through b(3) in
A second related art example is described in, for example, JP-A-10-257782, and is illustrated in
An operation of the second voltage command limiting means will be described by reference to the drawings.
Next, when “θ11≦30°” holds in step 8, θ11* is determined in step 9 from “θ11*=COS−(Vmax/|V1|)−30°”. In an analogous manner, when “θ11>30°” holds, θ11* is determined from “θ11*=COS−(Vmax/|V1|)−30°, and in both cases processing further proceeds to step 15. Next, also in the case where the first voltage command limiting means 102 is selected (“MODE 1=0” in step 3) or the second voltage command limiting means 103 is selected, when |V1| is determined to be smaller than Vmax in step 4, operations during steps 11 to 14 are performed in an analogous manner to the previous steps 5 to 8, thereby reaching step 15. In step 15, t0, t1 and t2 are calculated on the basis of the corrected voltage amplitude command |V1| and the corrected voltage phase command θ11*. In step 16, switching between DOWN mode and UP mode is effected. In steps 17 and 18, DOWN mode or UP mode is detected, thereby setting T0, T1, and T2. In step 19, T0, T1, and T2 are set to TU, TV, and TW with reference to θ1 on the basis of the table shown in
As described above, a line voltage exceeding a direct current bus voltage of the PWM inverter can be output; simultaneously, an intermediate state ranging from a sinusoidal output to an output of six-step voltage (rectangular output) is developed, thereby enabling a smooth transition.
However, as the first related art, an intermediate voltage during a transition from a sinusoidal voltage output to a six-step voltage output cannot be obtained; as a result, there arise problems such that smooth switching between modes is difficult, and that a control characteristic in a current control system, where a current control function is required, becomes unstable during a transitory period of switching.
Further, as the second related art, it has a problem that smooth transition switching to a six-step voltage output requires complicated processing including determination of switching, limitation on lengths of command voltage vectors, or correction of angles of vectors by calculating an arcsine and by reference to a table which stores lengths of vectors and corresponding angles.
The present invention has been conceived to solve the above problems and to provide a PWM inverter which enables smooth mode switching during transition from a sinusoidal voltage output to a six-step voltage output, and which can provide smooth mode switching by means of simple control processing.
In order to solve the above problem, claim 1 of the invention is characterized by a PWM inverter having PWM pulse output means for outputting a PWM pulse signal upon magnitude comparison of phase voltage commands with a carrier wave of a triangular or a saw-tooth waveform, wherein:
By means of the above means, within a range where amplitudes of line voltage commands corresponding to the phase voltage commands are not greater than a direct current bus voltage of the PWM inverter, the line voltage can be output in a sinusoidal wave; and even in the case where the amplitude of the line voltage command exceeds the direct current bus voltage, the line voltage having the direct current bus voltage as an upper limit thereof can be output (in this case, the output voltage is not sinusoidal); accordingly, even a voltage output higher than the direct current bus voltage can be output as an amplitude of the line voltage command (when viewed as an effective value of a fundamental wave component).
In the case of switching to effect transition to a six-step voltage output, smooth transition switching can also be enabled with regard to a voltage amplitude of the phase voltage commands. The reason for this is that there are provided a first region of up to 1/{square root}3 times a direct current bus voltage (when twice the value of the amplitude of the carrier wave is caused to correspond to the direct current bus voltage, the phase voltage commands is 2/{square root}3 times the carrier amplitude, and the same applies hereinafter) which is capable of outputting a sinusoidal wave voltage; a third region of 2/{square root}3 times the direct current bus voltage—where six-step voltage is output—or larger (4/{square root}3 times the carrier amplitude or larger); and an intermediate second region thereof.
Further, complicated processing is not required for implementing processing pertaining to the above means, and the above effects can be obtained only by means of simple processing.
Further, the invention defined in claim 2 is characterized in that the PWM inverter of claim 1 includes first voltage conversion means which limits the amplitude of the phase voltage commands to 4/{square root}3 times the amplitude of the carrier wave when the amplitude of the phase voltage commands is 4/{square root}3 times an amplitude of the carrier wave or larger.
In the case where the amplitude of the phase voltage commands is 2/{square root}3 times the direct current bus voltage or larger (the phase voltage commands are 4/{square root}3 times the carrier amplitude or larger), the line voltage command (instantaneous value) is always equal to or greater than the direct current bus voltage.
Therefore, limitation on the amplitude of the phase voltage commands to 4/{square root}3 times the amplitude of the carrier wave does not affect an output voltage of the PWM inverter; meanwhile, simplification of processing or the like in accordance with the above limitation enables an instantaneous response from a large voltage command to a small voltage command.
Further, the invention defined in claim 3 is characterized in that the PWM inverter of claim 1 includes second voltage conversion means which limits the amplitudes of the phase voltage commands to a predetermined value of 4/{square root}3 times the amplitude of the carrier wave or larger when the amplitudes of the phase voltage commands are 4 {square root}3 times an amplitude of the carrier wave or larger.
Even in the case where the amplitudes of the phase voltage commands are limited to a predetermined value of 4 {square root}3 times the amplitude of the carrier wave or larger, an effect analogous to that of claim 2 of the invention can be obtained.
Further, the invention defined in claim 4 is characterized in that the PWM inverter of claim 1 or claim 3 includes third voltage conversion means which converts the phase voltage commands to values obtained from multiplication of the phase voltage commands by {square root}3 when the amplitudes of the phase voltage commands are 2/{square root}3 times an amplitude of the carrier wave or larger.
A six-step voltage which serves as a maximum line voltage of the PWM inverter is 2/{square root}3 times a direct current bus voltage (when viewed as an amplitude value of a fundamental wave component). Therefore, in the case where a six-step voltage output is enabled when voltage amplitudes of the line voltage commands in accordance with the phase voltage commands are 2{square root}3 times the direct current bus voltage or larger; in other words, when the phase voltage commands (amplitude values) are 2/3 times the direct current bus voltage (the phase voltage commands are 4/3 times the carrier wave amplitude), the PWM inverter can output voltages which follow command voltages.
Because a six-step voltage output can be achieved when the phase voltage commands (amplitude values) are 4/{square root}3 times the amplitude of the carrier wave or larger, in order to obtain a six-step voltage output under phase voltage commands whose values are 4/3 times the carrier wave amplitude, the only requirement is to set as phase voltage commands values obtained by multiplication of the phase voltage commands by {square root}3. Meanwhile, such voltage conversion processing is performed only within a region where output of a sinusoidal voltage is impossible; in other words, a region where the amplitudes of the phase voltage commands are 2/{square root}3 times the amplitude of the carrier wave or larger.
Further, the invention defined in claim 5 is characterized in that first and third voltage conversion means, or second and third voltage conversion means, are formed from voltage conversion means 1, which is set as fourth voltage conversion means.
Further, the invention defined in claim 6 is characterized in that the first voltage conversion means of the PWM inverter of claim 2 limits the amplitude of the phase voltage commands to 4/{square root}3 times the amplitude of the carrier wave when the amplitudes of the line voltage obtained from the phase voltage commands are four times an amplitude of the carrier wave or larger.
Because the line voltage is {square root}3 times the phase voltage, with regard to the PWM inverter according to claim 2 where the amplitude of the phase voltage commands is used as a determination reference, an object of determination has been changed to the line voltage, and the determination reference has been increased by a factor of {square root}3.
Further, the invention defined in claim 7 is characterized in that the second voltage conversion means of the PWM inverter of claim 3 limits the amplitude of the phase voltage commands to a predetermined value of 4/{square root}3 times the amplitude of the carrier wave or larger when the amplitude of the line voltage obtained from the phase voltage commands is four times an amplitude of the carrier wave or larger.
The purport of the invention is analogous to that of claim 6.
Further, the invention defined in claim 8 is characterized in that the third voltage conversion means of the PWM inverter of claim 4 converts the phase voltage values into values obtained from multiplication of the phase voltage values by {square root}3 when the amplitude of the line voltage obtained from the phase voltage commands is two times an amplitude of the carrier wave or larger.
Meanwhile, among reference numerals in drawings, 1 denotes a voltage command shifter, 2 denotes a PWM signal generator, 3 denotes a carrier signal generator, 4 denotes a voltage command limiter, 5 denotes a voltage command multiplier, 11 denotes a commercial power source, 12 denotes a rectifier diode in a converter section, 13 through 18 denote IGBT transistors, 19 through 24 denote circulating diodes, 25 denotes a current detector, 26 denotes an electric motor, 29 denotes a smoothing capacitor, 101 denotes a PWM pattern generation section, 102 denotes a first voltage command limiter, 103 denotes a second voltage command limiter, 104 denotes a voltage-command-limiting-value switching section, and 105 denotes a mode determination section.
Next, embodiments of the present invention will be described with reference to the drawings.
When three-phase voltage commands for U-phase, V-phase and W-phase are supplied from a high-level controller, the voltage command shifter 1 compares absolute values (|Vru|, |Vrv|, |Vrw|) of the respective phase voltage commands (Vru, Vrv, Vrw), and selects a voltage command Vrx of a phase having the largest absolute value among the absolute values. Next, magnitudes of a maximum value (Cmax) and a minimum value (Cmin) of carrier signals obtained from the carrier signal generator 3 are compared with Vrx:
The PWM signal generator 2 compares a carrier wave from the carrier signal generator 3 with Vu, Vv, and Vw, thereby outputting PWM pulses of the respective phases.
By means of the foregoing operations, in the case where amplitude of the phase voltage commands becomes 4 {square root}3 times an amplitude of the carrier signals, and pulses generated by the PWM generator become six-step PWM pulses, automatic switching to six-step PWM can be achieved by merely increasing the amplitude of the phase voltage commands without requiring complicated calculations or special switching.
A sinusoidal wave is generally used for three-phase voltage commands supplied from a high-level controller; however, when a line voltage is designed so as to output a desired voltage, other waveforms may also be employed instead.
When three-phase voltage commands for U-phase, V-phase and W-phase are supplied from a high-level controller, the voltage command limiter 4 obtains a voltage amplitude of the phase voltage commands, and obtains an amplitude of carrier signals from the maximum value and the minimum value of the carrier signals from the carrier signal generator 3; and the amplitude of the phase voltage commands having an upper limit of 4/{square root}3 times the amplitude of the carrier signals is supplied to the voltage command shifter 1.
Operations of the voltage command shifter 1 and the PWM generator 2 are identical with those of the block diagram in
When the above limitations are imposed by the high-level controller, the voltage commands can be prevented from becoming excessively large; accordingly, a control response speed of the PWM inverter under a condition where the voltage commands must be decreased rapidly is improved. In the above, the voltage amplitude of the phase voltage command has been described as being obtained in the voltage command limiter 4; however, there may be adopted a configuration where an amplitude of the phase voltage commands is supplied from a high-level controller to the voltage command limiter 4. Further, no problem arises in integrating the voltage command limiter 4 into the voltage command shifter 1.
When three-phase voltage commands for U-phase, V-phase and W-phase are supplied from a high-level controller, the voltage command multiplier 5 obtains an amplitude Vpp of the phase voltage commands, thereby obtaining a maximum carrier signal value Cmax, a minimum value Cmin, and a differential value thereof Cdiff. When the amplitude Vpp of the phase voltage exceeds Cdiff/{square root}3, values (Vu′, Vv′, and Vw′)-which are obtained from multiplication of the respective phase voltage command values (Vru, Vrv, and Vrv) by {square root}3—are supplied to the voltage command shifter 1.
Operations of the voltage command shifter 1 and the PWM generator 2 are identical with those of the aforementioned block diagram in
In the example, multiplication is performed by the voltage command multiplier 5; however, such a multiplication adjustment can be performed elaborately by a high-level controller. When the above is adopted, linearity of voltage values which are actually output from the PWM inverter and voltage commands is further improved.
Further, the voltage command multiplier 5 may be integrated in the voltage command shifter 1.
Furthermore, the second embodiment and the third embodiment can be implemented in a combined manner.
The present invention has been described in detail and with reference to specific embodiments; however, as is apparent to one skilled in the art, various changes and modifications can be adopted without departing form the spirit and scope of the invention.
The present invention is based on Japanese Patent Application filed on Mar. 20, 2002 (Japanese Patent Application No.2002-078452), which is incorporated herein by reference.
As has been described, the present invention provides smooth mode switching during a transition from a sinusoidal voltage output to a six-step voltage output; and even in a current control system where current control function is required, favorable and stable control function can be obtained during the above transition.
Further, with regard to transition switching to a six-step voltage output, the invention does not require complicated processing including determination of switching, limitation on lengths of command voltage vectors, or correction of angles of vectors by calculating an arcsine and using a table which stores lengths of vectors and angles corresponding thereto; and such transition switching can be implemented rapidly through simple processing.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2002-078452 | Mar 2002 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP03/03267 | 3/18/2003 | WO |
