Claims
- 1. A control circuit for igniting an array of pyrotechnic devices each at a different array position, said circuit comprising:
- control means employing digital computer means responsive to an applied ignite command signal for selectively igniting said devices in a given ignition sequence; and
- means for causing the control means to interrupt the ignition of said devices prior to the completion of the ignition of all said devices in said sequence from a designated first device in the sequence leaving a portion of non-ignited devices in the sequence, and then selectively restart the ignition sequence from the first designated device of said sequence or from the next to be ignited device in the remainder of the non-ignited devices in the stopped sequence.
- 2. The circuit of claim 1 wherein said control means includes a central processor unit (CPU), said circuit including means responsive to said command signal for operating said CPU in a plurality of first periods in an ignition cycle of a given duration and for disabling said CPU in a plurality of second periods of said cycle, each said second period being between adjacent first periods, said first periods each having a duration substantially smaller than the duration of said cycle.
- 3. The circuit of claim 1 including memory means having a plurality of storage locations, each location for storing the address of at least one position of the array, said circuit including means for storing the addresses of different portions of the array at corresponding different memory locations.
- 4. The circuit of claim 3 wherein each said location at least one position corresponds to a given set of a plurality of array positions, said means for storing the addresses includes means for storing at a corresponding location the position of the device in the array which was last ignited.
- 5. A control circuit for igniting an array of pyrotechnic devices each at a different array position, said circuit comprising:
- control means including a normally disabled central processor unit (CPU) responsive to a command signal applied thereto for enabling the CPU and for generating a device ignite signal in an ignition cycle; and
- means for periodically enabling and disabling the CPU for the generation of said ignite signal in said ignition cycle in response to the receipt of said command signal such that the CPU draws negligible electrical power when disabled as compared to when enabled.
- 6. The circuit of claim 5 wherein said circuit includes means for operating said CPU in a plurality of enable first periods in said ignition cycle of a given duration and for disabling said CPU in a plurality of second disable periods of said cycle, said second period being between adjacent first periods, said first periods each having a duration substantially smaller than the duration of said cycle.
- 7. The circuit of claim 6 wherein the total time duration of all said first periods is substantially less than the given duration of said ignition cycle.
- 8. The circuit of claim 6 wherein the duration of each said first periods is less than 100 microseconds and the duration of said ignition cycle is greater than one second.
- 9. The circuit of claim 6 wherein the CPU has a plurality of input and output ports, said input ports including reset, signal validation and enable ports for receiving corresponding CPU reset, command signal and CPU enable signals for activating said CPU, said output ports including a device address code port for receiving a CPU generated coded signal manifesting a device address and a control port for receiving a CPU generated control signal manifesting the time of the generation of said device ignite signal.
- 10. The circuit of claim 9 wherein the control signal is encoded, said circuit including decode means for decoding said coded device address signal and for decoding said control signal, and matrix means responsive to said decoded device signal and decoded control signal for generating said device ignite signal.
- 11. The circuit of claim 10 wherein said CPU includes circuit means responsive to said ignite signal applied to said enable port for disabling said CPU.
- 12. The circuit of claim 9 including means for validating the command signal as valid and for applying a valid/invalid signal to said validation port for respectively enabling said CPU only when said command signal is valid.
- 13. The circuit of claim 9 wherein the CPU is enabled when electrical power is applied to the circuit and disabled when power is removed, said circuit including a resettable program reset circuit having selectable first and second states for resetting the CPU in the first state to successively generate an address signal manifesting the address of the next device to be ignited in a given sequence when the CPU is successively enabled, disabled and then enabled by selectively applying and removing said power or in the second state to restart the addressing of the devices at the beginning of the sequence after the CPU is disabled.
- 14. The circuit of claim 10 wherein the circuit includes a programmable RAM for storing the addresses of the devices and resettable circuits coupled to the CPU, said CPU including means responsive to electrical power applied to said circuit for generating in an initial period prior to said first periods and prior to said ignition cycle a first set of CPU operating signals including signals for configuring the output ports, resetting said plurality of resettable circuits and for loading the RAM with the address of the next to be ignited device in a sequence.
- 15. The circuit of claim 14 including means for generating an audio warning signal prior to generating the ignite signal, said CPU including means for testing the command signal as valid and for causing said audio signal to be generated in response to said decoded control signal applied thereto if the command signal is valid in an initial one of said first periods.
- 16. The circuit of claim 15 wherein the CPU and the circuit include means such that in a next successive first period following said initial one of said first periods the CPU verifies the audio signal has been generated, causes the decode means to generate a decoded device address to thereby generate in response to the decoded address and decoded control signal the device ignite signal.
- 17. The circuit of claim 16 wherein the decode means and means for validating the command include reset means, the CPU including means such that in a further successive first period following said next successive period the CPU updates the RAM with the address of the next to be ignited device, resets said decode means, returns to the initial one of said first periods, resets the means for validating the command signal as valid and then enters the disable mode for receipt of the next command signal.
Parent Case Info
This is a division of patent application Ser. No. 145,499 filed Nov. 1, 1993 now U.S. Pat. No. 5,450,686 which is a division of patent application Serial No. 877,809 filed May 4, 1992 now U.S. Pat. No. 5,284,094 which is a division of patent application Ser. No. 419,549 filed Oct. 10, 1989 now U.S. Pat. No. 5,157,222.
Of interest is patent application Ser. No. 383,650 filed Jul. 24, 1989 entitled Electrically Activated Detonator with Pyrotechnic Device Receiving Terminals and Method of Making in the name of Joseph L. La Mura et al. and assigned to the assignee of the present invention now U.S. Pat. No. 4,951,570.
US Referenced Citations (7)
Divisions (3)
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Number |
Date |
Country |
Parent |
145499 |
Nov 1993 |
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Parent |
877809 |
May 1992 |
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Parent |
419549 |
Oct 1989 |
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