Quad rate transmitter equalization

Abstract

An integrated circuit provides equalized outputs. Main data and equalization data is produced at one fourth of the output data rate, and multiplexed onto an output node at the output data rate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an integrated circuit with quad rate transmitter equalization;

FIG. 2 shows a timing diagram;

FIG. 3 show a quad rate equalization output circuit;

FIG. 4 show a quad rate equalization output circuit with programmable multiplexer control;

FIG. 5 shows a flowchart in accordance with various embodiments of the present invention; and

FIGS. 6 and 7 show diagrams of electronic systems in accordance with various embodiments of the present invention.

Claims

1. A circuit comprising: a first current mode driver to drive output data on an output node at an output data rate;a first four-to-one multiplexer coupled to provide the output data to the first current mode driver;a second current mode driver to drive equalization data on the output node at the output data rate;a second four-to-one multiplexer coupled to provide the equalization data to the second current mode driver; anda logic circuit to drive the first and second four-to-one multiplexers with output data and equalization data, respectively, at one fourth the output data rate.

2. The circuit of claim 1 further comprising a programmable multiplexer control circuit to steer the first and second four-to-one multiplexers.

3. The circuit of claim 2 wherein the programmable multiplexer control circuit is coupled to be responsive to a configuration register.

4. The circuit of claim 1 further comprising a third current mode driver to drive additional equalization data on the output node at the output data rate.

5. The circuit of claim 4 further comprising a third four-to-one multiplexer coupled to provide the additional equalization data to the third current mode driver.

6. The circuit of claim 1 further comprising a parallel-to-serial converter circuit to receive data at less than one fourth the output data rate, and coupled to provide data to the logic circuit at one fourth the output data rate.

7. A memory device comprising: an output node;an output circuit to drive data on the output node at an output data rate;a memory core circuit to source memory data at less than one fourth the output data rate;a parallel-to-serial converter coupled to receive the memory data and source intermediate data at one fourth the output data rate; anda logic circuit coupled to receive the intermediate data and coupled to provide the output circuit with output data at one fourth the output data rate, and further coupled to provide the output circuit with equalization data at one fourth the output data rate.

8. The memory device of claim 7 wherein the output circuit includes a first four-to-one multiplexer coupled to receive the output data from the logic circuit and a first current mode driver to drive the output data on the output node at the output data rate.

9. The memory device of claim 8 wherein the output circuit further includes a second four-to-one multiplexer coupled to receive the equalization data from the logic circuit and a second current mode driver to drive the equalization data on the output node at the output data rate.

10. The memory device of claim 9 further comprising a programmable multiplexer control circuit to steer the first and second four-to-one multiplexers.

11. The memory device of claim 10 wherein the programmable multiplexer control circuit is coupled to be responsive to a configuration register.

12. The memory device of claim 7 further comprising at least one additional four-to-one multiplexer and at least one additional current mode driver to drive additional equalization data on the output node at the output data rate.

13. A method comprising: receiving data from a core of an integrated circuit and arranging the data into groups of four at a data rate of N/4;generating equalization data in groups of four at the data rate of N/4;multiplexing the data onto a single output pad at a data rate of N; andmultiplexing the equalization data onto the output pad at the data rate of N.

14. The method of claim 13 wherein multiplexing the data and multiplexing the equalization data are performed in response to programmable multiplexer signals.

15. The method of claim 13 further comprising multiplexing additional equalization data onto the output pad at the data rate of N.

16. The method of claim 13 wherein receiving data comprises: receiving data from a memory core at a data rate of less than N/4; andconverting the data from the memory core into groups of four at a data rate of N/4.

17. An electronic system comprising: an antenna;a radio frequency circuit coupled to the antenna;a controller coupled to the radio frequency circuit; anda memory device coupled to the controller, the memory device including an output node, an output circuit to drive data on the output node at an output data rate, a memory core circuit to source memory data at less than one fourth the output data rate, a parallel-to-serial converter coupled to receive the memory data and source intermediate data at one fourth the output data rate, and a logic circuit coupled to receive the intermediate data and coupled to provide the output circuit with output data at one fourth the output data rate, and further coupled to provide the output circuit with equalization data at one fourth the output data rate.

18. The electronic system of claim 17 wherein the output circuit includes a first four-to-one multiplexer coupled to receive the output data from the logic circuit and a first current mode driver to drive the output data on the output node at the output data rate.

19. The electronic system of claim 18 wherein the output circuit further includes a second four-to-one multiplexer coupled to receive the equalization data from the logic circuit and a second current mode driver to drive the equalization data on the output node at the output data rate.

20. The electronic system of claim 19 wherein the memory device further comprises a programmable multiplexer control circuit to steer the first and second four-to-one multiplexers.